DETAILED ACTION
This application is responsive to the following: the application filed on March 21, 2025 and the information disclosure statements filed on July 3, 2025 and December 4, 2025.
Claims 1-30 are pending. 1, 8, 16, 21, and 25 are Independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on July 3, 2025 and December 4, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objection
Independent claims 1, 8, 21 and 25 each spell out “access counter initialization (ACI). Independent claim 16 only uses ACI. Applicant should include the basis for acronyms in each independent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-11, 13-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (US 20210158853 A1).
Regarding Independent Claim 1, Wang teaches An apparatus (Fig. 2: 200) comprising:
a plurality of word lines (Fig. 1: K word lines) each coupled to a respective plurality of memory cells (Fig. 1: Storage cells), wherein a portion of the plurality of memory cells (Fig. 1: Storage cells) are counter memory cells (Fig. 1: 110B; para 18 “extraordinary storage cells 110B may be arranged to accumulate and store the respective access counts of the plurality of word lines”) configured to store a plurality of access count values associated with a number of times a respective word line of the plurality of word lines (Fig. 1: K word lines) has been accessed; and
an activation counter initialization (ACI) control circuit (Fig. 1: 113) configured to initialize the plurality of access count values as part of an ACI operation (para 39 “the WAC control unit 113 may clear at least one portion (e.g. a portion or all) of word line access count data, and more particularly, clear all information in the (K*N) extraordinary storage cells 110B, to reset the counter values”).
Regarding Claim 2, Wang teaches the limitations of Claim 1. Wang further teaches comprising a counter control circuit (Fig. 1: 116) configured to:
read the respective access count value when one word line of the plurality of word lines (Fig. 1: K word lines) is activated (para 26 “the WAC control unit 113 may utilize the counter such as the N-bits counter 116 to read the set of bit information (e.g. the N bits of word line access count data) from the extraordinary page buffer such as the N-bits extraordinary page buffer 114.”), update the access count value (para 27 “the WAC control unit 113 may utilize the counter such as the N-bits counter 116 to update, more particularly, increase, a counter value CNT(k) indicated by the set of bit information”), and write the access count value back to the counter memory cells (Fig. 1: 110B; para 18 “extraordinary storage cells 110B may be arranged to accumulate and store the respective access counts of the plurality of word lines”) of the word line as part of an access operation (para 31 “the WAC control unit 113 may utilize the counter such as the N-bits counter 116 to write a set of updated bit information”); or
write an initialization value to the counter memory cells (Fig. 1: 110B; para 18 “extraordinary storage cells 110B may be arranged to accumulate and store the respective access counts of the plurality of word lines”) as part of the ACI operation.
Regarding Claim 6, Wang teaches the limitations of Claim 1. Wang further teaches comprising an address counter configured (Fig. 2: 201) to generate an ACI row address responsive to the count increment signal as part of the ACI operation.
Regarding Claim 7, Wang teaches the limitations of Claim 1. Wang further teaches comprising a refresh control circuit (Fig. 2: 201) configured to determine if the respective word line is an aggressor word line based, in part, on the access count value (para 30 “he WAC control unit 113 may issue (e.g. generate or output, more particularly, generate and output) an alarm, where Step S40A is entered afterward. For example, the memory module 100 may notify the host system of the event of the counter value CNT(k) reaching the predetermined counter value threshold TH_CNT, but the present invention is not limited thereto.”).
Regarding Independent Claim 8, Wang teaches An apparatus (Fig. 2: 200) comprising:
a memory array comprising a plurality of word lines (Fig. 1: K word lines) each associated with one of a plurality of access count values;
an activation counter initialization (ACI) controller (Fig. 1: 113) configured to provide a count increment signal and an ACI signal during an ACI operation;
an address counter (Fig. 2: 201) configured to generate a row address responsive to the count increment signal;
a row decoder (Fig. 2: 202) configured to activate one or more of the word lines (Fig. 1: K word lines) based on the row address; and
a counter control circuit (Fig. 1: 116) configured to access each of the word lines (Fig. 1: K word lines) and initialize the plurality of access count values to an initialization value (para 39 “the WAC control unit 113 may clear at least one portion (e.g. a portion or all) of word line access count data, and more particularly, clear all information in the (K*N) extraordinary storage cells 110B, to reset the counter values”).
Regarding Claim 9, Wang teaches the limitations of Claim 8. Wang further teaches a counter mapping circuit configured to map an ACI address to a plurality of row addresses to initialize multiple count values at a time (para 39 “According to some embodiments, when there is a need, the WAC control unit 113 may clear at least one portion (e.g. a portion or all) of word line access count data, and more particularly, clear all information in the (K*N) extraordinary storage cells 110B, to reset the counter values {CNT(0), CNT(1), . . . , CNT(K−1)} to be zero.”).
Regarding Claim 10, Wang teaches the limitations of Claim 9. Wang further teaches wherein the address counter and the counter mapping circuit are existing components of a refresh control circuit (Fig. 2: 201).
Regarding Claim 11, Wang teaches the limitations of Claim 9. Wang further teaches wherein the address counter is configured to generate a refresh address when not in an ACI mode (para 44 “a central control unit 201 for controlling access of the memory banks 210, 220, . . . , and 280 according to external commands, addresses, etc. from the host system,”).
Regarding Claim 13, Wang teaches the limitations of Claim 8. Wang further teaches wherein the initialization value is a predetermined value (para 29 “the WAC control unit 113 may reset (e.g. clear) the counter value CNT(k) to be an initial value such as zero”).
Regarding Claim 14, Wang teaches the limitations of Claim 8. Wang further teaches wherein the ACI operation is triggered by an external command (Fig. 2: REFA_EN).
Regarding Claim 15, Wang teaches the limitations of Claim 8. Wang further teaches wherein the external command is a refresh command (Fig. 2: REFA_EN).
Regarding Independent Claim 16, Wang teaches A method comprising:
accessing a word line (Fig. “K word lines”) of a memory associated with ACI address counter (Fig. 2: 201);
initializing an access counter value along the accessed word line (para 39 “the WAC control unit 113 may clear at least one portion (e.g. a portion or all) of word line access count data, and more particularly, clear all information in the (K*N) extraordinary storage cells 110B, to reset the counter values”);
iterating the ACI address counter value (Fig. 3: S30).
Regarding Claim 18, Wang teaches the limitations of Claim 16. Wang further teaches comprising enabling an ACI mode (Fig. 2: REFS_EN, REFA_EN).
Claims 21, 24-25, and 28-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al (US 20250006242 A1).
Regarding Independent Claim 21, Kim teaches A method comprising:
enabling a first op-code (Fig. 6: ISG2) of a register (Fig 6: 420) to enable per-row activation counting on a memory device;
setting a second op-code (Fig. 6: ISG1) of a register to an active value to enable an access counter initialization (ACI) mode;
issuing refresh commands to perform ACI operations (Fig. 6: REF_ADDR);
checking a third op-code of the register; and
setting the second op-code to an inactive value responsive to the third op-code being active. (para 73 “he comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Regarding Claim 24, Kim teaches the limitations of Claim 21. Kim further teaches comprising only issuing refresh commands after setting the second op-code to the active value until setting the second op-code to the inactive value. (para 73 “he comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Regarding Independent Claim 25, Kim teaches an apparatus (Fig. 2: 200) comprising:
a memory array (Fig. 1: 290_1) comprising a plurality of word lines;
a mode register (Fig. 6: 420) including a register with a first, second, and third operational code (op-code); and
an access counter initialization (ACI) control circuit (Fig. 1: 230) configured to enter an ACI mode responsive to the second op-code being set (ISG1), configured to perform ACI operations on the plurality of word lines responsive to refresh commands in the ACI mode, and configured to set the third op-code responsive to completing ACI operations on the plurality of word lines. (para 73 “he comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Regarding Claim 28, Wang teaches the limitations of Claim 25. Wang further teaches wherein the ACI control circuit is configured to reset the value of the third op-code responsive to the second op-code being set. (para 73 “he comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Regarding Claim 29, Wang teaches the limitations of Claim 28. Wang further teaches wherein the ACI control circuit is configured to reset the value of the third op-code responsive to the first op-code being disabled. (para 48 “When the refresh control circuit 230 outputs the refresh address REF_ADDR to the plurality of row decoders 250, the row decoder 250 may perform refresh on the plurality of memory cell arrays 290 based on the refresh address REF_ADDR. When refreshing is performed on the plurality of memory cell arrays 290, the refresh control circuit 230 may initialize at least one of the access count and victim point.”)
Regarding Claim 30, Wang teaches the limitations of Claim 25. Wang further teaches comprising a refresh control circuit configured to enable per-row activation counting (PRAC) responsive to the first op-code being set (para 59 “The register 320 manages the access count of rows,”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 12, and 19-20 and are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20210158853 A1) in view Kim et al (US 20250006242 A1).
Regarding Claim 5, Wang teaches the limitations of Claim 1. Wang fails to teach a mode register.
Kim teaches a mode register (Fig 6: 420) configured to store an ACI status, wherein the ACI control circuit is configured to set the ACI status to an active level after initializing each of the plurality of access count values. (para 73 “the comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Wang refers to a host external to the memory apparatus that performs a lot of the functions of checking values and in turn responding with signals that control the apparatus described in wang. However, being able to control these functions internally would improve operations speeds. Thus, incorporating registers such as those taught in Kim internal to the memory apparatus allows for more efficient performing of operations without having to contact the host.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kim to the teachings of Wang to teach a memory apparatus with a mode register, which manages access counts of WL and controls when initialization operations begin that initialize access count values stored in cells within the memory array.
Regarding Claim 12, Wang teaches the limitations of Claim 8. Claim 12 is rejected for the same reasons as claim 5.
Regarding Claim 19, Wang teaches the limitations of Claim 18. Wang fails to teach a mode register.
Kim teaches setting a mode register bit to indicate the ACI mode is enabled (para 73 “the comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”).
Wang refers to a host external to the memory apparatus that performs a lot of the functions of checking values and in turn responding with signals that control the apparatus described in wang. However, being able to control these functions internally would improve operations speeds. Thus, incorporating registers such as those taught in Kim internal to the memory apparatus allows for more efficient performing of operations without having to contact the host.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kim to the teachings of Wang to teach a memory apparatus with a mode register, which manages access counts of WL and controls when initialization operations begin that initialize access count values stored in cells within the memory array.
Regarding Claim 20, Wang teaches the limitations of Claim 19. Wang fails to teach a mode register.
Kim teaches comprising setting a second mode register bit to indicate the ACI mode is complete. (para 73 “the comparator 430 may check the count value of the register counter 420 when the first internal signal ISG1 is received. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (e.g., ‘0’), and output a trigger signal TRS when the values match.”)
Claims 3-4 and 17 and are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20210158853 A1) in view of Rooney (US 20220383933 A1)
Regarding Claim 3, Wang teaches the limitations of Claim 1. Wang fails to teach wherein a next word line is activated before a first word line is deactivated as a part of the ACI operation.
Rooney teaches wherein a next word line is activated before a first word line is deactivated as a part of the ACI operation (Fig. 6: 610, 620, 630).
Its well understood in the art that activating and performing operations on multiple word lines simultaneously allows for faster operations in memory. Thus, improving speed of the device.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Rooney to Wang to produce a method of initializing cells storing access count data within a memory.
Regarding Claim 4, Wang and Rooney teach the limitations of Claim 3. Rooney further teaches wherein the ACI control circuit is further configured to activate the next word line after a first time and deactivate the first word line after a second time, wherein the second time is longer than the first time (Fig. 6: 610, 620, 630).
Regarding Claim 17, Wang teaches the limitations of Claim 16. Wang further teaches firing a target section's sense amplifiers, wherein the target section comprises a plurality of word lines (Fig. 1: K word lines);
driving an initialization value onto a plurality of counter bit lines (Fig. 3: S40B); and
Wang fails to teach activating each word line of the plurality of word lines one-by-one, wherein each word line is activated before a previous word line is deactivated.
Rooney teaches activating each word line of the plurality of word lines one-by-one, wherein each word line is activated before a previous word line is deactivated (Fig. 6: 610, 620, 630).
It’s well understood in the art that activating and performing operations on multiple word lines simultaneously allows for faster operations in memory. Thus, improving speed of the device.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Rooney to Wang to produce a method of initializing cells storing access count data within a memory.
Allowable Subject Matter
22-23, and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 22 is allowable for requiring the limitation that commands refresh commands are issued at twice the normal refresh rate. Both Wang and Kim are silent with respect to the relative refresh rates of the apparatuses disclosed. Therefore, this claim would be allowable if written in independent form.
Claim 23 is allowable for requiring the limitation that activation counts are not tracked when the memory is initializing count values. Both Wang and Kim silent with respect to whether or not activation counts are counted during this operation.
Claim 26 is allowable for teaching that normal refresh operations cannot occur when the count storing cells are being initialized. Both Wang and Kim are silent with respect to normal refresh operations occurring while this is simultaneously occurring.
Claim 27 is allowable for requiring the limitation that modes in registers are set after a full refresh cycle. Both Wang and Kim fail to teach conditions based on full refresh cycle.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
