DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim(s) 1-19 do not use “means for” (or “step for”) language, or generic placeholders for "means” coupled with functional language without recitation of sufficient structure for carrying out the claimed functions and therefore do not invoke 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-8 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimano (US 2009/0295955 A1) in view of Brown et al. (US 8,836,066 B1) in view of Maehashi et al. (WO 2023/131996 A1) in view of Sekine (US 2023/0163229 A1).
The following rejections provide citations to English language equivalent Maehashi (US 2024/0357259 A1). See MPEP 901.05(II).[claim 1]
Regarding claim 1, Shimano discloses a conversion apparatus (e.g. Figure 1) comprising:
a pixel (Figure 1; Paragraph 0029); and
an output unit configured to output data according to an output signal of the pixel (Figure 1, LVDS interface 5),
wherein the output unit includes a first circuit and a second circuit configured to operate at a speed faster than a speed of the first circuit (Figure 2; Paragraph 0011, 0036-0038).
However, Shimano does not teach that the pixel includes an avalanche photodiode.
Brown teaches the use of an avalanche photodiode for image sensors to increase the sensitivity of the image sensor and allow for improved low-light imaging (c. 3, ll. 27-36). Therefore, it would have been obvious to use an avalanche photodiode in the pixels of the image sensor of Shimano so that sensitivity can be increased resulting in improved low-light imaging.
However, Shimano in view of Brown does not teach that an absolute value of a threshold voltage of a first transistor which constitutes the first circuit is larger than an absolute value of a threshold voltage of a second transistor which constitutes the second circuit.
Shimano teaches transistors which provide operation in a high-speed mode and a low-speed mode (Figure 2; Paragraph 0011, 0036-0038). Maehashi teaches designing transistors to have high driving power which can contribute to high-speed operation by lowering the threshold voltage of the transistor (Paragraphs 0080-0081). Maehashi further teaches that lowering the threshold voltage may increase off-leakage current of the transistor and results in a drop in driving power (Paragraph 0081).
Since the second circuit requires a higher-speed operation than the first circuit, it would have been obvious to adjust the threshold voltage of the second circuit of Shimano in view of Brown to be lower than that of the first circuit so that a high driving power may be achieved by the second circuit, while simultaneously suppressing an increase in off-leakage current in the first circuit as taught by Maehashi.
However, Shimano in view of Brown in view of Maehashi does not explicitly disclose that the pixel includes a circuit configured to process a signal according to an output of the avalanche diode.
Sekine discloses a similar pixel device including avalanche photodiodes and further discloses the inclusion of a circuit to process the output of the photodiode (Figure 2, Item 30). Therefore, it would have been obvious to provide a processing circuit as taught by Sekine in the pixels of Shimano in view of Brown in view of Maehashi so that a processed signal, such as a photon count or a time-to-digital conversion to measure timing of a pulse detected by the pixel may be output (e.g. Paragraph 0201).[claim 4]
Regarding claim 4, Maehashi discloses wherein in the first transistor, an impurity concentration at a drain end portion of an impurity having a conductivity type that is the same as a conductivity type of the first transistor is a first concentration, and in the second transistor, an impurity concentration at a drain end portion of an impurity having a conductivity type that is the same as a conductivity type of the second transistor is a second concentration that is higher than the first concentration (Paragraphs 0087-0088).[claim 5]
Regarding claim 5, Maehashi discloses wherein in the first transistor, an impurity concentration in a channel region of an impurity having a conductivity type that is the same as a conductivity type of the first transistor is a third concentration, and in the second transistor, an impurity concentration in a channel region of an impurity having a conductivity type that is the same as a conductivity type of the second transistor is a fourth concentration that is higher than the third concentration (Paragraphs 0087-0088).[claim 6]
Regarding claim 6, Maehashi discloses wherein the first transistor has a first channel length, and the second transistor has a second channel length that is longer than the first channel length (Paragraphs 0087-0088)[claim 7]
Regarding claim 7, Maehashi discloses wherein a gate insulating film of the first transistor is thicker than a gate insulating film of the second transistor (Paragraphs 0087-0088).[claim 8]
Regarding claim 8, Shimano discloses wherein the second circuit includes a serializer configured to convert parallel data into serial data (e.g. Paragraphs 0069-0071).[claim 15]
Regarding claim 15, see the rejection of claim 1 above.[claim 16]
Regarding claim 16, Shimano in view of Brown in view of Maehashi does not disclose wherein a first substrate to which the avalanche diode is provided and a second substrate to which the circuit and the output unit are provided are laminated to each other.
However, Sekine additionally discloses that the avalanche diode and the processing circuit may be placed on separate substrates which are laminated together (Paragraph 0058-0059). Using separate substrates in this manner would allow for a greater area for the avalanche photodiodes.
Therefore, it would have been obvious to use separate substrates as claimed so that a greater area may be dedicated to the avalanche photodiodes.[claim 17]
Regarding claim 17, Shimano in view of Brown in view of Maehashi in view of Sekine discloses a system comprising the conversion apparatus according to claim 1 (see rejection above).
Sekine additionally discloses a processing apparatus configured to process a signal output from a conversion apparatus (e.g.. Figure 21, 306) which allows for image information to be processed for storage or display (Paragraphs 0147-0151) or a moving object including a processing unit configured to process the output from a conversion device to determine distances which allows the moving object to be controlled (Figure 24; Paragraphs 0169-0179) .
Therefore, it would have been obvious to include an additional processing apparatus the system so that image information captured by the pixels may be processed for storage or display or to allow a moving object to be controlled.[claim 18]
Regarding claim 18, see the rejection of claim 17 above.[claim 19]
Regarding claim 19, see the rejection of claim 17 above and note that Sekine discloses at least a display, storage or mechanical apparatus as claimed.
Claim(s) 2-3, 9 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimano (US 2009/0295955 A1) in view of Brown et al. (US ) in view of Maehashi et al. (WO 2023/131996 A1) in view of Sekine (US 2023/0163229 A1) in view of Official Notice.
The following rejections provide citations to English language equivalent Maehashi (US 2024/0357259 A1). See MPEP 901.05(II).[claim 2]
Regarding claim 2, Shimano describes a power supply (Paragraph 0033) but does not explicitly disclose that the power supply powers the pixel.
Official Notice is taken that it is well known in the art to use a common power supply for powering components of a system (such as a positive voltage or ground). Therefore, it would have been obvious to use the power supply to also power the pixels to reduce the number of voltages necessary to be created to power the system. [claim 3]
Regarding claim 3, Shimano in view of Brown in view of Maehashi in view of Sekine does not explicitly disclose wherein a clock signal is input to a switch provided between the avalanche diode and a node from which a power source to be applied to the avalanche diode is supplied.
However, Sekine does disclose the inclusion of a quench circuit for an avalanche photodiode which may be a MOS transistor (Figure 3, 24; Paragraph 0052).
Official Notice is taken that is well known in the art to activate a MOS transistor to turn on or turn off using a clock signal. Therefore, it would have been obvious to include a MOS transistor quench circuit taught by Sekine and to drive the transistor using a clock signal so that the change in avalanche current generated by the avalanche diode of Shimano in view of Brown may be converted into a voltage signal and to return the voltage supplied to the photoelectric conversion element to the voltage by flowing a current corresponding to the voltage drop by the quenching operation by activating the MOS transistor (Sekine, Paragraph 0052). [claim 9]
Regarding claim 9, Shimano discloses wherein the output unit includes a pixel signal output circuit, and a second power source voltage having a magnitude different from that of the first power source voltage is supplied to the pixel signal output circuit (Figure 2, Vdd2).[claim 12]
Regarding claim 12, Shimano in view of Brown in view of Maehashi in view of Sekine does not explicitly disclose wherein an absolute value of a threshold voltage of a fourth transistor which constitutes the circuit in the pixel is larger than the absolute value of the threshold voltage of the second transistor.
However, it is noted that the pixel circuit includes a processing circuit such as a counter or time-to-digital converter (Sekine; Paragraph 0201). Official Notice is taken that it is well known in the art to form counters or time-to-digital converters using transistors so that the counter/time-to-digital converters may be integrated into a semiconductor device. Therefore, it would have been obvious to form counters or time-to-digital converters using transistors so that the counter/time-to-digital converters may be integrated into a semiconductor device.
Applying the teachings of Maehashi, it would have been obvious to set the threshold voltage to a value lower than that of the second transistor so that off-leakage current of the transistors making up the counter or time-to-digital converters may be reduced.[claim 13]
Regarding claim 13, Maehashi discloses wherein in the second transistor, an impurity concentration in a channel region of an impurity having a conductivity type that is the same as a conductivity type of the second transistor is a fourth concentration, and in the fourth transistor, an impurity concentration in a channel region of an impurity having a conductivity type that is the same as a conductivity type of the fourth transistor is a sixth concentration that is lower than the fourth concentration (Paragraphs 0087-0088).[claim 14]
Regarding claim 14, applying the teachings of Maehashi, it would have been obvious to set the threshold voltages of the first and fourth transistors equal so that off-leakage current may be similarly reduced. Additionally would have been obvious to one having ordinary skill in the art to set the threshold values to be equal since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.[claims 10-11]
Regarding claims 10-11 the prior art does not teach or reasonably suggest the conversion apparatus according to Claim 9, wherein an absolute value of a threshold voltage of a third transistor which constitutes the pixel signal output circuit is larger than the absolute value of the threshold voltage of the second transistor.
While Shimano and Maehashi disclose a conversion apparatus including transistors having different threshold voltages, the prior art does not teach or reasonably suggest the particular combinations recited wherein an absolute value of a threshold voltage of a third transistor which constitutes the pixel signal output circuit is larger than the absolute value of the threshold voltage of the second transistor.
While Shimano discloses an output unit in which it would have been obvious to use transistors (Shimano, Figure 2), since the output unit would be required to perform at high-speeds when a high-speed mode is selected it would not have been obvious to sue a larger threshold voltage than the second transistor as claimed when applying the teachings of Maehashi.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ardelean et al. US 2026/0101126 A1
Hirai US 2025/0158608 A1
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/Timothy J Henn/Primary Examiner, Art Unit 2639
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