CTNF 19/087,368 CTNF 96224 DETAILED ACTION The instant application having Application No. 19/087,368 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/087,368 filed 3/21/2025 is a Continuation of 17/219,327 filed 3/31/2021, now U.S. Patent #12260111. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/2/2025 and 8/12/2025 are being considered by the examiner. Claim Language Claims 17 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger. The limitations in the claims following “in response to an event…” are not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger. The method may never be required to execute the condition because the claim recites a temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends amending the claim to provide for detecting an event and performing the subsequent actions in response to the detecting of the event. See Ex parte Schulhauser , Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz , Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original. Claim Objections 07-29-01 AIA Claim s 16 and 19 are objected to because of the following informalities: For claim 16, “a erasure block size” should be amended to read “[[a]] an erasure block size”. For claim 19, “senor data packets” should be amended to read “[[senor]] sensor data packets” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2-3, 9-16, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claims 2-3, there is insufficient antecedent basis for the term “the processor”. With respect to claim 11, there is insufficient antecedent basis for the term “the plurality of sensors”. 07-35-01 Claims 9, 12, and 20 contain the trademark/trade name non-volatile memory express (NVMe). Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe non-volatile memory express and, accordingly, the identification/description is indefinite. Where claims 9, 12, and 20 further recite a protocol of a non-volatile memory express, said protocol is indefinite because a protocol of non-volatile memory express, as recited, may be interpreted as claiming a protocol including new protocols of non-volatile memory express that may come to include a different scope in the future, beyond what has been considered by the applicant. Therefore, one of ordinary skill in the arts may be unable to determine the metes and bounds of the claimed invention. Claims 10 and 13-16 are rejected for being dependent on a rejected claim. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-19 of U.S. Patent No. 12260111 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application . Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995. Claims 1-10 of instant application 19/087,368 are rejected over claims 1-9 of U.S. Patent No. 12260111, corresponding to application 17/219,327. Claims 11-16 of instant application 19/087,368 are rejected over claims 10-15 of U.S. Patent No. 12260111. Claims 17-20 of instant application 19/087,368 are rejected over claims 16-19 of U.S. Patent No. 12260111. The double patenting rejection above applies to claims 1-20 . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 3-4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) . For claim 1, 1. A system, comprising: a plurality of sensors; and a data recorder, having a volatile memory; and a non-volatile memory comprising a file system , [Golov teaches a system comprising a data recorder, sensors, volatile memory, and non-volatile memory (para. 8-9, 12, 35-36; fig. 2 and associated paragraphs)] wherein the data recorder is configured to, in response to an event, store sensor data collected by the plurality of sensors into files organized under the file system . [Golov teaches a nonvolatile buffer for storing sensor data from multiple sensors (para. 12-14), where data in the nonvolatile buffer can be flushed into a nonvolatile storage in response to an event (para. 18)] Golov does not explicitly disclose, but Yamada discloses: a non-volatile memory comprising a file system ; files organized under the file system. [Golov teaches transferring sensor data from a nonvolatile buffer to a nonvolatile storage responsive to an event, but does not explicitly recite storing data as files; Yamada teaches a recording apparatus controlled by a CPU or system controller (Yamada: para. 62), the recording device storing image data from a camera unit as image files in a ring buffer of a nonvolatile memory, and, responsive to an event, transferring image files to a non-volatile buffer region of the nonvolatile memory (para. 49-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for storing image data produced by a plurality of sensors of the vehicle, wherein image data is organized into frame units and written as moving image data files into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage of continuously generated sensor data). (MPEP 2143) As per claim 3, Golov in view of Yamada teaches claim 1 as shown above and further teaches: 3. The system of claim 1, wherein the processor is configured to receive outputs from the plurality of sensors and generate sensor data packets written into the volatile memory. [Golov teaches storing data from sensors in a volatile memory (Golov: para. 12-13); Yamada teaches a processor-controlled recording apparatus, wherein image data from a camera unit is stored in a volatile memory as frames (packets) (para. 2-3, 46, 48-53, 62)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for storing image data produced by a plurality of sensors of the vehicle, wherein image data is organized into frame units and written as moving image data files into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage of continuously generated sensor data). (MPEP 2143) As per claim 4, Golov in view of Yamada teaches claim 1 as shown above and further teaches: 4. The system of claim 1, further comprising a processor configured to implement the file system mounted in a file system region of the non-volatile memory, [Yamada teaches a system comprising image recording apparatus storing image files from a ring buffer of nonvolatile memory to a nonvolatile buffer region (file system region) of the nonvolatile memory as shown above (see claim 1; para. 49-53, 56, 63-66, 69-71) and a CPU for controlling the recording apparatus (para. 62)] wherein the data recorder is further configured to: record outputs from the plurality of sensors via the volatile memory into a buffer region of the non-volatile memory in a cyclic way, and, in response to the event, retrieve the sensor data from the buffer region and store the sensor data into the files organized under the file system mounted in the file system region. [Golov teaches storing data from sensors in a volatile memory and flushing data responsive to an event (see claim 1 above; Golov: para. 12-14); Yamada teaches a volatile memory for storing data from a camera unit (Yamada: para. 48-53; fig. 2 and associated paragraphs; see para. 52-53 on processing image data in frame units for generating moving image file comprising frames and using the volatile memory for storage) and configured to write moving image files generated from the data into the ring buffer region of nonvolatile memory a file at a time and, in response to an event, transferring the moving image files to the nonvolatile buffer region (file system region) of the nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for storing image data produced by a plurality of sensors of the vehicle, wherein image data is organized into frame units and written as moving image data files into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage of continuously generated sensor data). (MPEP 2143) As per claim 11, 11. A device, comprising: a volatile memory; a non-volatile memory partitioned into a plurality of regions comprising a file system region and a buffer region ; and a processor configured to: [Golov teaches a system comprising a data recorder, sensors, volatile memory, and non-volatile memory (para. 8-9, 12; fig. 2 and associated paragraphs; see para. 35-36 for a processor)] store sensor data packets from the volatile memory in the buffer region in a cyclic way , each of the sensor data packets comprising data from one of the plurality of sensors; [Golov teaches a volatile buffer and a nonvolatile buffer for storing sensor data from multiple sensors (para. 9, 12-14), where the nonvolatile buffer can be flushed into a nonvolatile storage in response to an event (para. 18)] Golov does not explicitly disclose, but Yamada discloses: partitioned into a plurality of regions comprising a file system region and a buffer region ; in the buffer region in a cyclic way ; and in response to an event, retrieve sensor data from the buffer region and store the sensor data into files organized under a file system mounted in the file system region. [Golov teaches transferring sensor data from a nonvolatile buffer to a nonvolatile storage responsive to an event, but does not explicitly recite storing data as files and storing sensor data from the volatile memory to the buffer region; Yamada teaches a recording device controlled by a CPU or system controller (Yamada: para. 62), the device comprising a volatile memory for storing data from a camera unit (Yamada: para. 48-53; fig. 2 and associated paragraphs; see para. 52-53 on processing image data in frame units for generating moving image file comprising frames and using the volatile memory for storage) and configured to write moving image files generated from the data into the ring buffer region of nonvolatile memory a file at a time and, in response to an event, transferring the moving image files to the nonvolatile buffer region (file system region) of the nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for processing and storing image data produced by a plurality of sensors of the vehicle, wherein image data is used to generate image data files stored into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage and access of continuously generated sensor data). (MPEP 2143) 07-21-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chahwan et al. (US 20180074728 A1) . As per claim 2, Golov in view of Yamada teaches claim 1 as shown above and further teaches: 2. The system of claim 1, the volatile memory comprises a dynamic random access memory, and the non- volatile memory comprises a flash memory. [Golov teaches the volatile memory implemented as a dynamic RAM and the non-volatile memory being a flash memory (para. 13-14); Yamada also teaches a flash memory used as non-volatile memory (para 56)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for storing image data produced by a plurality of sensors of the vehicle, wherein image data is organized into frame units and written as moving image data files into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage of continuously generated sensor data). (MPEP 2143) Golov in view of Yamada does not explicitly disclose, but Chahwan discloses: wherein the processor comprises a system on chip, [While Golov teaches that its disclosures may be implemented using Application-Specific Integrated Circuit or Field-Programmable Gate Array, Golov’s teaching does not explicitly classify its disclosures to be implemented within a system on chip; Chahwan teaches a controller comprising processors which may include Application-Specific Integrated Circuit, Field-Programmable Gate Array, or System on a Chip (para. 18)] Golov, Yamada, and Chahwan are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Chahwan, to modify the disclosures by Golov in view of Yamada to include additional disclosures by Chahwan since they both teach storage of data, wherein Chahwan is directed towards improvements in reliability of the data stored (para. 2-3). Therefore, it would be applying a known technique (implementing a vehicle data capture device to include a controller comprising a processor that may include a system on a chip) to a known device (memory device for storing sensor information from a vehicle, wherein the memory device’s processes may be carried out by a processor) ready for improvement to yield predictable results (memory device for storing sensor information from a vehicle, wherein the memory device’s processes may be carried out by a processor including a system on a chip in order to provide for greater modularity). (MPEP 2143) 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) . As per claim 5, Golov in view of Yamada teaches claim 4 as shown above. It does not explicitly disclose, but Chou discloses: 5. The system of claim 4, wherein the volatile memory is configured into a first buffer and a second buffer; and the processor is configured to fill first sensor data packets into the first buffer to generate a first sensor data slice and then fill second data packets into the second buffer to generate a second send data slice. [Golov in view of Yamada teaches processing and storing data received from sensors in a working memory comprising a volatile memory in generating moving image files (sensor data slice) comprising frames (packets) (Yamada: 48-53; fig. 2 and associated paragraphs) and respectively writing moving image files a file at a time into the ring buffer region of nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64); Chou teaches allocating a plurality of image buffers for transfer, wherein, after one image buffer is filled, a second image buffer may be assigned to be filled (para. 23-24; figs. 1-2 and associated paragraphs), wherein the frames filling the image buffer may also correspond to sensor data packets and the batch of frames filled into the image buffer may also correspond to sensor data slice.] Golov, Yamada, and Chou are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Chou, to modify the disclosures by Golov in view of Yamada to include additional disclosures by Chou since they both teach data storage, wherein Chou is directed towards software efficiency in video recording (para. 5). Therefore, it would be applying a known technique (allocating respective image buffers to be filled with image frames and transferring a filled image buffer) to a known device (device configured to process and store sensor data in volatile memory for generating moving image files comprising frames and individually writing the moving image files to nonvolatile memory) ready for improvement to yield predictable results (device processing and storing sensor data in volatile memory, wherein respective buffers are allocated to be filled with frames for respective moving image files prior for transfer to nonvolatile memory in order to provide for improved memory management in saving and transferring image files). (MPEP 2143) 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of Brailovskiy et al. (US 10447926 B1) . As per claim 6, Golov in view of Yamada in view of Chou teaches claim 5 as shown above. It does not explicitly disclose, but Brailovskiy discloses: 6. The system of claim 5, wherein each of the first sensor data slice and the second data slice includes an identification and a timestamp. [Brailovskiy teaches stitching of captured video data frames and transmission of the processed video data for storage (col. 8, lines 17-64) and further teaches each video frame (packet) to contain metadata including information such as identification of the camera capturing the frame, frame number, and timestamp, wherein the stitched video data may correspond to sensor data slice (col. 3, lines 46-60; col. 5, line 50 – col. 6, lines 12; col. 13, lines 33-49; col. 23, lines 30-32), wherein the identification may correspond to the identification of the camera, a timestamp of the plurality of timestamps in the video may correspond to the timestamp] Golov, Yamada, Chou, and Brailovskiy are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou and Brailovskiy, to modify the disclosures by Golov in view of Yamada in view of Chou to include additional disclosures by Brailovskiy since they both teach storage of data, wherein Brailovskiy is directed towards more efficient coordination of generating the video data being stored (col. 23, lines 33-37). Therefore, it would be applying a known technique (providing information for video frames stitched together to form video data, including timestamp, frame number, and identification of the source camera) to a known device (memory device storing image files comprising frames) ready for improvement to yield predictable results (memory device storing image files comprising frames, the frames comprising information including timestamp, frame number, and identification of the source camera in order to provide for improved tracking of units of image produced from multiple sources). (MPEP 2143) 07-21-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of Brailovskiy et al. (US 10447926 B1) in view of De Ambroggi et al. (US 20080306723 A1) . As per claim 7, Golov in view of Yamada in view of Chou in view of Brailovskiy teaches claim 6 as shown above. It does not explicitly disclose, but De Ambroggi discloses: 7. The system of claim 6, wherein concurrently with filling the second data packets into the second buffer, the processor is configured to read the first sensor data slice from the first buffer and write the first sensor data slice into the buffer region in the non-volatile memory. [Golov in view of Yamada in view of Chou in view of Brailovskiy as shown above teaches filling a plurality of buffers for transfer to nonvolatile memory; De Ambroggi discloses a configuration including at least two buffers, where a first buffer is filled to be transferred and, when the first buffer is full, filling the second buffer while the data from the first buffer is being transferred (para. 35, 39)] Golov, Yamada, Chou, Brailovskiy, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of Brailovskiy and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Chou in view of Brailovskiy to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (operating two buffers by writing to a first buffer while transferring from a second buffer) to a known device (memory device that uses a plurality of buffers for storing and transferring data) ready for improvement to yield predictable results (memory device that uses a plurality of buffers for storing and transferring data, where the buffers may be operated so that a buffer may be written to while another buffer is being transferred in order to provide for improved consistency of data write speed). (MPEP 2143) 07-21-aia AIA Claim 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of Brailovskiy et al. (US 10447926 B1) in view of in view of in view of De Ambroggi et al. (US 20080306723 A1) in view of Morabad et al. (US 20220004333 A1) . As per claim 8, Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi teaches claim 7 as shown above and further teaches: 8. The system of claim 7, wherein the buffer region is identified via a namespace allocated in the non-volatile memory; and [De Ambroggi teaches allocating different address spaces for different portions of a non-volatile memory (para. 33, lines 1-17)] Golov, Yamada, Chou, Brailovskiy, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of Brailovskiy and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Chou in view of Brailovskiy to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (using different address space for different non-volatile memory portions) to a known device (device that uses buffers for writing data to a non-volatile memory comprising a ring buffer region and another region for accommodating data moved from the ring buffer region) ready for improvement to yield predictable results (device that uses buffers for writing data to a non-volatile memory, wherein different address space are assigned for different non-volatile memory portions in order to provide for improved modularity in treatment of different non-volatile memory regions). (MPEP 2143) Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi does not explicitly disclose, but Morabad discloses: a location to write the first sensor data slice in the non-volatile memory is identified via an address of logical block addressing (LBA) in the namespace. [Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi as shown above teaches a memory controller utilized for storing image files to nonvolatile memory, in a recording apparatus controlled by a CPU/system controller (Yamada: para. 56, 62); Morabad teaches an NVMe controller that writes data according to write requests issued by a host, a write request comprising the namespace and the logical blocks in the SSD where the data should be written (para. 22, 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, Chou, Brailovskiy, De Ambroggi, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi and Morabad, to modify the disclosures by Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller writing data to a location identified by an LBA in a namespace) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory) ready for improvement to yield predictable results (device including an NVME controller configured to write data to a specified region of a non-volatile memory identified by an LBA and a namespace to allow for improved referencing of write locations). (MPEP 2143) As per claim 9, Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi in view of Morabad teaches claim 8 as shown above and further teaches: 9. The system of claim 8, further comprising: a solid state drive having the non-volatile memory and a host interface, the host interface implementing a non-volatile memory express (NVMe) protocol for communication with the processor. [Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi as shown above teaches a memory controller utilized for storing image files to nonvolatile memory, in a recording apparatus controlled by a CPU/system controller (Yamada: para. 56, 62); Morabad teaches a solid state storage device with a NVME controller and an interface (host interface) that may communicate with a host using means including NVMe protocol (para. 22, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, Chou, Brailovskiy, De Ambroggi, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi and Morabad, to modify the disclosures by Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller using a host interface with NVMe protocol for communication with a host) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory) ready for improvement to yield predictable results (device controlled by a system controller communicating with a NVMe controller through an interface with NVMe protocol for utilizing more uniform communication standards). (MPEP 2143) As per claim 10, Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi in view of Morabad teaches claim 9 as shown above and further teaches: 10. The system of claim 9, wherein a size of the first sensor data slice is configured to be aligned with a block size of memory addressable via logical block addressing (LBA) in the namespace. [Morabad teaches that its write request specifies the number of logical blocks that are to be written to a logical address (para. 22, 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs), where data written at locations referenced in units of logical blocks would necessarily align with logical blocks sizes] Golov, Yamada, Chou, Brailovskiy, De Ambroggi, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi and Morabad, to modify the disclosures by Golov in view of Yamada in view of Chou in view of Brailovskiy in view of De Ambroggi to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller writing data to a location identified by an LBA in a namespace) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory) ready for improvement to yield predictable results (device including an NVME controller configured to write data to a specified region of a non-volatile memory identified by an LBA and a namespace to allow for improved referencing of write locations). (MPEP 2143) 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Morabad et al. (US 20220004333 A1) . As per claim 12, Golov in view of Yamada claim 11 as shown above. It does not explicitly disclose, but Morabad discloses: 12. The device of claim 11, wherein the non-volatile memory is configured in a solid state drive; and the processor is configured read the sensor data from the buffer region and write the files using a non-volatile memory express (NVMe) protocol. [Golov in view of Yamada teaches a memory controller utilized for storing image files to nonvolatile memory, in a recording apparatus controlled by a CPU/system controller (Yamada: para. 56, 62), where the image files are configured to be copied (read and write) from ring buffer (buffer region) to non-volatile buffer (file system region) (Yamada: para. 63-66, 69-71), and where the system controller (the processor) performs copying using the memory controller (Yamada: para. 155; fig. 16 and associated paragraphs); Morabad teaches a solid state storage device with a NVMe controller and an interface (host interface) that may communicate with a host using means including NVMe protocol (para. 22, 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Morabad, to modify the disclosures by Golov in view of Yamada to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (SSD comprising a NVMe controller and host interface based on NVMe for communication with a host) to a known device (device controlled by a system controller, the system controller configured to copy data from a region of a nonvolatile memory to a second region using a memory controller) ready for improvement to yield predictable results (device controlled by a system controller, the system controller configured to copy data from a region of a nonvolatile memory to a second region using a NVMe controller which communicates with the system controller through NVMe protocol; doing so would provide for improved command processing time over alternatives such as SATA). (MPEP 2143) 07-21-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Morabad et al. (US 20220004333 A1) in view of Chahwan et al. (US 20180074728 A1) . As per claim 13, Golov in view of Yamada in view of Morabad teaches claim 12 as shown above and further teaches: 13. The device of claim 12, the volatile memory includes a dynamic random access memory; and the non- volatile memory includes a flash memory. [Golov teaches the volatile memory implemented as a dynamic RAM and the non-volatile memory being a flash memory (para. 13-14); Yamada also teaches a flash memory used as non-volatile memory (para 56)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for processing and storing image data produced by a plurality of sensors of the vehicle, wherein image data is used to generate image data files stored into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage and access of continuously generated sensor data). (MPEP 2143) Golov in view of Yamada in view of Morabad does not explicitly disclose, but Chahwan discloses: wherein the processor includes a system on chip; [While Golov teaches that its disclosures may be implemented using Application-Specific Integrated Circuit or Field-Programmable Gate Array, Golov’s teaching does not explicitly classify its disclosures to be implemented within a system on chip; Chahwan teaches a controller comprising processors which may include Application-Specific Integrated Circuit, Field-Programmable Gate Array, or System on a Chip (para. 18)] Golov, Yamada, Morabad, and Chahwan are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Morabad and Chahwan, to modify the disclosures by Golov in view of Yamada in view of Morabad to include disclosures by Chahwan since they both teach storage of data, wherein Chahwan is directed towards improvements in reliability of the data stored (para. 2-3). Therefore, it would be applying a known technique (implementing a vehicle data capture device to include a controller comprising a processor that may include a system on a chip) to a known device (memory device for storing sensor information from a vehicle, wherein the memory device’s processes may be carried out by a processor) ready for improvement to yield predictable results (memory device for storing sensor information from a vehicle, wherein the memory device’s processes may be carried out by a processor including a system on a chip in order to provide for greater modularity). (MPEP 2143) 07-21-aia AIA Claim s 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Morabad et al. (US 20220004333 A1) in view of Chahwan et al. (US 20180074728 A1) in view of Chou et al. (US 20190348074 A1) in view of De Ambroggi et al. (US 20080306723 A1) . As per claim 14, Golov in view of Yamada in view of Morabad in view of Chahwan teaches claim 13 as shown above. It does not explicitly disclose, but Chou discloses: 14. The device of claim 13, wherein the volatile memory is configured to provide a first buffer and a second buffer operable in parallel ; [Golov in view of Yamada in view of Morabad in view of Chahwan teaches processing and storing data received from sensors in a working memory comprising a volatile memory in generating moving image files (sensor data slice) comprising frames (Yamada: 48-53; fig. 2 and associated paragraphs) and respectively writing moving image files a file at a time into the ring buffer region of nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64; see claim 11 above); Chou teaches allocating a plurality of image buffers for transfer, wherein, after one image buffer is filled, a second image buffer may be assigned to be filled (para. 23-24; figs. 1-2 and associated paragraphs), wherein the frames filling the image buffer may correspond to sensor data packets and the batch of frames filled into the image buffer may correspond to sensor data slice.] Golov, Yamada, Morabad, Chahwan, and Chou are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Morabad in view of Chahwan and Chou, to modify the disclosures by Golov in view of Yamada in view of Morabad in view of Chahwan to include additional disclosures by Chou since they both teach data storage, wherein Chou is directed towards software efficiency in video recording (para. 5). Therefore, it would be applying a known technique (allocating respective image buffers to be filled with image frames and transferring a filled image buffer) to a known device (device configured to process and store sensor data in volatile memory for generating moving image files comprising frames and individually writing the moving image files to nonvolatile memory) ready for improvement to yield predictable results (device processing and storing sensor data in volatile memory, wherein respective buffers are allocated to be filled with frames for respective moving image files prior for transfer to nonvolatile memory in order to provide for improved memory management in saving and transferring image files). (MPEP 2143) Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou does not explicitly disclose, but De Ambroggi discloses: operable in parallel; when the first buffer is being written into to generate a sensor data slice, the second buffer is readable in parallel to write a sensor data slice into the buffer region in the non-volatile memory. [Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou as shown above teaches filling a plurality of buffers for transfer to nonvolatile memory; De Ambroggi discloses a configuration including at least two buffers, where a first buffer is filled to be transferred and, when the first buffer is full, filling the second buffer while the data from the first buffer is being transferred (para. 35, 39)] Golov, Yamada, Morabad, Chahwan, Chou, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (operating two buffers by writing to a first buffer while transferring from a second buffer) to a known device (memory device that uses a plurality of buffers for storing and transferring data) ready for improvement to yield predictable results (memory device that uses a plurality of buffers for storing and transferring data, where the buffers may be operated so that a buffer may be written to while another buffer is being transferred in order to provide for improved consistency of data write speed). (MPEP 2143) As per claim 15, Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi teaches claim 14 as shown above and further teaches: 15. The device of claim 14, wherein the file system region and the buffer region are configured as two namespaces allocated from the non-volatile memory; and [De Ambroggi teaches allocating different address spaces for different portions of a non-volatile memory (para. 33, lines 1-17)] the processor is configured to identify a location to write a sensor data slice from one of the first buffer and the second buffer in a namespace of the buffer region at a location identified using an address of logical block addressing (LBA). [Morabad teaches a solid state storage device with a NVMe controller and an interface (host interface) that may communicate with a host (processor) using means including NVMe protocol, where the controller may receive write request including the namespace and the logical blocks in the SSD where the data should be written (para. 22, 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Morabad, to modify the disclosures by Golov in view of Yamada to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller writing data to a location identified by an LBA in a namespace) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory and comprising respective regions corresponding to respective namespaces) ready for improvement to yield predictable results (device including an NVME controller configured to write data to a specified region of a non-volatile memory identified by an LBA and a namespace to allow for improved referencing of write locations). (MPEP 2143) Golov, Yamada, Morabad, Chahwan, Chou, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (using different address space for different non-volatile memory portions) to a known device (device that uses a volatile buffer for writing data to a non-volatile memory comprising a ring buffer region and another region for accommodating data moved from the ring buffer region) ready for improvement to yield predictable results (device that uses a volatile buffer for writing data to a non-volatile memory, wherein different address space are assigned for different non-volatile memory portions in order to provide for improved modularity in treatment of different non-volatile memory regions). (MPEP 2143) 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Morabad et al. (US 20220004333 A1) in view of Chahwan et al. (US 20180074728 A1) in view of Chou et al. (US 20190348074 A1) in view of De Ambroggi et al. (US 20080306723 A1) in view of Zhang et al. (US 20180121351 A1) . As per claim 16, Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi teaches claim 14 as shown above and further teaches: 16. The device of claim 14, wherein each of the first buffer and the second buffer is configured to have a storage capacity for a sensor data slice having a size that is multiple of a block size of memory addressable using the logical block addressing (LBA) in the namespace of the buffer region [Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi as shown above teaches a NVMe controller utilized for storing image files to nonvolatile memory, in a recording apparatus controlled by a CPU/system controller, and storing sensor data slices (image files) in buffers allocated in volatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; Chou: para. 23-24), the writes through NVMe controller involving write requests indicating a specified number (multiple) of logical blocks for write data (i.e. sensor data slice, image file) (Morabad: para. 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Morabad, to modify the disclosures by Golov in view of Yamada to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller writing data to a location identified by an LBA in a namespace) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory and comprising respective regions corresponding to respective namespaces) ready for improvement to yield predictable results (device including an NVME controller configured to write data to a specified region of a non-volatile memory identified by an LBA and a namespace to allow for improved referencing of write locations). (MPEP 2143) Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi does not explicitly disclose, but Zhang discloses: and multiple of a erasure block size of the non-volatile memory. [Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi as shown above teaches image files (sensor data slice) corresponding to a specified number of logical blocks stored in one or more buffers; Zhang teaches a logical block to correspond to at least one physical block, and data writes corresponding to the logical block being written to the at least one physical block which corresponds to the logical block (para. 11, 142-144, 150; claim 1); Zhang also teaches that erasure of data is carried out on physical block increments (para. 5, 133)] Golov, Yamada, Morabad, Chahwan, Chou, De Ambroggi, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi and Zhang, to modify the disclosures by Golov in view of Yamada in view of Morabad in view of Chahwan in view of Chou in view of De Ambroggi to include additional disclosures by Zhang since they both teach data storage, wherein Zhang is directed towards improved memory performance (para. 3-6). Therefore, it would be applying a known technique (associating a logical block with at least one physical block, storing data corresponding to a logical block in the at least one associated physical block) to a known device (device associating write data with a specified number of logical blocks) ready for improvement to yield predictable results (device associating write data with a specified number of logical blocks and the physical blocks corresponding to the specified number of logical blocks to enable efficient data access and storage of data in a nonvolatile storage medium). (MPEP 2143) 07-21-aia AIA Claim s 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of De Ambroggi et al. (US 20080306723 A1) . As per claim 17, 17. A method, comprising: operating, by a processor of a data recorder, ; and in response to an event, retrieving sensor data from the cyclic buffer region and storing the sensor data into files organized under the file system mounted in the file system region . [Golov teaches a system comprising a data recorder, sensors, volatile memory, and non-volatile memory (para. 8-9, 12; fig. 2 and associated paragraphs; see para. 35-36 for a processor); Golov teaches a volatile buffer and a cyclic nonvolatile buffer for storing sensor data from multiple sensors (para. 9, 12-14), where the nonvolatile buffer can be flushed into a nonvolatile storage in response to an event (para. 18)] Golov does not explicitly disclose, but Yamada discloses: a file system mounted in a file system region of a non-volatile memory of the data recorder; ; files organized under the file system mounted in the file system region [Golov teaches transferring sensor data from a cyclic nonvolatile buffer to a nonvolatile storage responsive to an event, but does not explicitly recite storing data as files; Yamada teaches a recording device controlled by a CPU or system controller (Yamada: para. 62), the device comprising a volatile memory for storing data from a camera unit (Yamada: para. 48-53; fig. 2 and associated paragraphs; see para. 52-53 on processing image data in frame units for generating moving image file comprising frames and using the volatile memory for storage) and configured to write moving image files generated from the data into the ring buffer region of nonvolatile memory a file at a time and, in response to an event, transferring the moving image files to the nonvolatile buffer region (file system region) of the nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for processing and storing image data produced by a plurality of sensors of the vehicle, wherein image data is used to generate image data files stored into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage and access of continuously generated sensor data). (MPEP 2143) Golov in view of Yamada does not explicitly disclose, but Chou discloses: generating, in a first buffer configured in a volatile memory of the data recorder, a first sensor data slice including first outputs from a plurality of sensors; [Golov in view of Yamada teaches processing and storing data received from sensors in a working memory comprising a volatile memory in generating moving image files (sensor data slice) comprising frames (Yamada: 48-53; fig. 2 and associated paragraphs) and respectively writing moving image files a file at a time into the ring buffer region of nonvolatile memory (Yamada: para. 52-53, 56, 63-66, 69-71; figs. 2, 3A-3C and associated paragraphs; see para. 124-125, 63-64); Chou teaches allocating a plurality of image buffers for transfer, wherein, after one image buffer is filled with frames, a second image buffer may be assigned to be filled (para. 23-24; figs. 1-2 and associated paragraphs), wherein the batch of frames filled into an image buffer may also correspond to sensor data slice.] Golov, Yamada, and Chou are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Chou, to modify the disclosures by Golov in view of Yamada to include additional disclosures by Chou since they both teach data storage, wherein Chou is directed towards software efficiency in video recording (para. 5). Therefore, it would be applying a known technique (allocating respective image buffers to be filled with image frames and transferring a filled image buffer) to a known device (device configured to process and store sensor data in volatile memory for generating moving image files comprising frames and individually writing the moving image files to nonvolatile memory) ready for improvement to yield predictable results (device processing and storing sensor data in volatile memory, wherein respective buffers are allocated to be filled with frames for respective moving image files prior for transfer to nonvolatile memory in order to provide for improved memory management in saving and transferring image files). (MPEP 2143) Golov in view of Yamada in view of Chou does not explicitly disclose, but De Ambroggi discloses: flushing the first sensor data slice from the first buffer into a cyclic buffer region of the non-volatile memory of the data recorder, in parallel with generating, in a second buffer configured in the volatile memory, a second sensor data slice using second outputs from the plurality of sensors; [Golov in view of Yamada in view of Chou as shown above teaches filling a plurality of buffers for transfer to a ring buffer region of nonvolatile memory; De Ambroggi discloses a configuration including at least two buffers, where a first buffer is filled to be transferred and, when the first buffer is full, filling the second buffer while the data from the first buffer is being transferred (para. 35, 39)] Golov, Yamada, Chou, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Chou to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (operating two buffers by writing to a first buffer while transferring from a second buffer) to a known device (memory device that uses a plurality of buffers for storing and transferring data) ready for improvement to yield predictable results (memory device that uses a plurality of buffers for storing and transferring data, where the buffers may be operated so that a buffer may be written to while another buffer is being transferred in order to provide for improved consistency of data write speed). (MPEP 2143) As per claim 18, Golov in view of Yamada in view of Chou in view of De Ambroggi teaches claims 17 as shown above and further teaches: 18. The method of claim 17, further comprising: flushing the second first sensor data slice from the second buffer into the cyclic buffer region of the non-volatile memory of the data recorder, in parallel with generating, in the first buffer configured in the volatile memory, a third sensor data slice using third outputs from the plurality of sensors. [Golov in view of Yamada in view of Chou in view of De Ambroggi as shown above discloses a configuration including at least two buffers, where a first buffer is filled to be transferred and, when the first buffer is full, filling the second buffer while the data from the first buffer is being transferred (para. 35, 39), the disclosure comprising a loop, where, after the second buffer has been filled and starts transferring data, which follows the first buffer being filled and transferring data, the first buffer again starts being filled with data as the second buffer is transmitting data (para. 39)] Golov, Yamada, Chou, and De Ambroggi are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou and De Ambroggi, to modify the disclosures by Golov in view of Yamada in view of Chou to include additional disclosures by De Ambroggi since they both teach data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (operating two buffers by writing to a first buffer while transferring from a second buffer) to a known device (memory device that uses a plurality of buffers for storing and transferring data) ready for improvement to yield predictable results (memory device that uses a plurality of buffers for storing and transferring data, where the buffers may be operated so that a buffer may be written to while another buffer is being transferred in order to provide for improved consistency of data write speed). (MPEP 2143) 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of De Ambroggi et al. (US 20080306723 A1) in view of Brailovskiy et al. (US 10447926 B1) . As per claim 19, Golov in view of Yamada in view of Chou in view of De Ambroggi teaches claims 18 as shown above and further teaches: 19. The method of claim 18, wherein the buffer region has a capacity to store more than two sensor data slices; [Golov in view of Yamada in view of Chou in view of De Ambroggi as shown above teaches using respective buffers of volatile memory for storing respective moving image files (sensor data slice) comprising frames (see claims 17-18 above; Yamada: para. 52-53, 56, 63-66, 69-71; Chou: para. 23-24); Yamada teaches the ring buffer of nonvolatile memory (buffer region) to comprise a plurality of moving image files (para. 63-65; see figs. 3A-3C showing more than two image files)] wherein each respective sensor data slice has a predetermined size and a structure identified by a schedule [Golov in view of Yamada in view of Chou in view of De Ambroggi as shown above teaches buffers allocated for the files (Chou: para. 23-24), where the size of the buffers may correspond to the predetermined size; further, it would have been obvious for one of ordinary skill in the arts, before the effective filing date of the claimed invention, to have modified the size of data associated with the data as recited in the instant claim in order to support optimal transfer and storage sizes. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please also see MPEP 2144.05 II. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989) (Claimed ratios were obvious as being reached by routine procedures and producing predictable results)] Golov and Yamada are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov and Yamada, to modify the disclosures by Golov to include additional disclosures by Yamada since both Golov and Yamada teach storage of data, wherein Yamada is directed towards improvements in storage and use of drive data (para. 74-75). Therefore, it would be applying a known technique (device for generating and writing image files comprising frames into a ring buffer, which are moved to another region in response to an event) to a known device (memory device for storing data produced by a plurality of sensors of the vehicle) ready for improvement to yield predictable results (memory device for processing and storing image data produced by a plurality of sensors of the vehicle, wherein image data is used to generate image data files stored into a non-volatile ring buffer, which are moved to another region of the non-volatile in response to an event, in order to provide for improved reliability and space efficiency in storage and access of continuously generated sensor data). (MPEP 2143) Golov, Yamada, and Chou are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada and Chou, to modify the disclosures by Golov in view of Yamada to include additional disclosures by Chou since they both teach data storage, wherein Chou is directed towards software efficiency in video recording (para. 5). Therefore, it would be applying a known technique (allocating respective image buffers to be filled with image frames and transferring a filled image buffer) to a known device (device configured to process and store sensor data in volatile memory for generating moving image files comprising frames and individually writing the moving image files to nonvolatile memory) ready for improvement to yield predictable results (device processing and storing sensor data in volatile memory, wherein respective buffers are allocated to be filled with frames for respective moving image files prior for transfer to nonvolatile memory in order to provide for improved memory management in saving and transferring image files). (MPEP 2143) Golov in view of Yamada in view of Chou in view of De Ambroggi does not explicitly disclose, but Brailovskiy discloses: wherein each respective sensor data slice has a predetermined size and a structure identified by a schedule specifying association of senor data packets, sensors that provide the sensor data packets, and timing of generation of the sensor data packets relative to a timestamp of the respective sensor data slice. [Brailovskiy teaches stitching of captured video data frames and transmission of the processed video data for storage (col. 8, lines 17-64) and further teaches each video frame (data packet) to contain metadata including information such as identification of the camera capturing the frame (sensors providing the sensor data packet), frame number (association of sensor data packets), and timestamp, wherein the stitched video data may correspond to sensor data slice (col. 3, lines 46-60; col. 5, line 50 – col. 6, lines 12; col. 13, lines 33-49; col. 23, lines 30-32), wherein the timestamp of each frame would necessarily be indicative of the timing of generation of the frame relative to timestamps of other frames in the sensor data slice] Golov, Yamada, Chou, De Ambroggi, and Brailovskiy are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of De Ambroggi and Brailovskiy, to modify the disclosures by Golov in view of Yamada in view of Chou in view of De Ambroggi to include additional disclosures by Brailovskiy since they both teach storage of data, wherein Brailovskiy is directed towards more efficient coordination of generating the video data being stored (col. 23, lines 33-37). Therefore, it would be applying a known technique (providing information for video frames stitched together to form video data, including timestamp, frame number, and identification of the source camera) to a known device (memory device storing image files comprising frames) ready for improvement to yield predictable results (memory device storing image files comprising frames, the frames comprising information including timestamp, frame number, and identification of the source camera in order to provide for improved tracking of units of image produced from multiple sources). (MPEP 2143) 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 20190287319 A1) in view of Yamada et al. (US 20190230325 A1) in view of Chou et al. (US 20190348074 A1) in view of De Ambroggi et al. (US 20080306723 A1) in view of Brailovskiy et al. (US 10447926 B1) in view of Gieseke (US 20190095121 A1) in view of Morabad et al. (US 20220004333 A1) . As per claim 20, Golov in view of Yamada in view of Chou in view of De Ambroggi teaches claims 19 as shown above and further teaches: allocating a first namespace from the non-volatile memory for the buffer region; allocating a second namespace from the non-volatile memory for the file system region; and [De Ambroggi teaches allocating different address spaces for different portions of a non-volatile memory (para. 33, lines 1-17)] Golov, Yamada, Chou, De Ambroggi, and Brailovskiy are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy, to modify the disclosures by Golov in view of Yamada in view of Chou in view of De Ambroggi in view of Brailovskiy to include additional teachings by De Ambroggi since the references are directed towards data storage, wherein De Ambroggi is directed towards improved memory performance (para. 4, 24, 38). Therefore, it would be applying a known technique (using different address space for different non-volatile memory portions) to a known device (device that uses buffers for writing data to a non-volatile memory comprising a ring buffer region and another region for accommodating data moved from the ring buffer region) ready for improvement to yield predictable results (device that uses a volatile buffer for writing data to a non-volatile memory, wherein different address space are assigned for different non-volatile memory portions in order to provide for improved modularity in treatment of different non-volatile memory regions). (MPEP 2143) Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy does not explicitly disclose, but Gieseke discloses: 20. The method of claim 19, further comprising, prior to the event: writing each sensor data slice flushed from the volatile memory into an empty slot in the buffer region before the buffer region is full; erasing, after the buffer region is full, an oldest data slice from the buffer region to provide an empty slot to accommodate a sensor data slice to be flushed from the volatile memory; [Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy discloses a ring buffer with areas each capable of storing one moving image file (sensor data slice) and overwriting an area with new moving image file (see Yamada: para. 65); while Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy does not explicitly disclose erasing a slot prior to writing new data, Gieseke discloses writing data from one ring buffer to another circular buffer, and, when a receiving ring buffer is full, erasing the oldest data to provide space for the newest data (para. 24)] Golov, Yamada, Chou, De Ambroggi, Brailovskiy, and Gieseke are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy and Gieseke, to modify the disclosures by Golov in view of Yamada in view of Chou in view of De Ambroggi in view of Brailovskiy to include teachings by Gieseke since the references are directed towards data storage, wherein Gieseke is directed towards improved memory utilization and management (para. 3). Therefore, it would be applying a known technique (deleting the oldest item in a circular buffer when the circular buffer is full to accommodate new items) to a known device (device that uses a volatile buffer for writing data to a non-volatile memory comprising a ring buffer region) ready for improvement to yield predictable results (device that uses a volatile buffer for writing data to a non-volatile memory comprising a ring buffer region, where an oldest entry in the ring buffer region may be deleted to accommodate new writes when the ring buffer region is full; doing so would provide for improved write latency). (MPEP 2143) Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy in view of Gieseke does not explicitly disclose, but Morabad discloses: accessing the buffer region and the file system region using logical block addressing (LBA) addresses in the first namespace and the second namespaces and a non-volatile memory express (NVMe) protocol. [Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy in view of Gieseke as shown above teaches a memory controller utilized for storing image files to nonvolatile memory, in a recording apparatus controlled by a CPU/system controller (Yamada: para. 56, 62); Morabad teaches an NVMe controller that writes data according to write requests issued by a host, where a write request contains the namespace and the logical blocks in the SSD where the data should be written (para. 22, 57, 24, 41, 127, 129; figs. 2, 6 and associated paragraphs)] Golov, Yamada, Chou, De Ambroggi, Brailovskiy, Gieseke, and Morabad are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy in view of Gieseke and Morabad, to modify the disclosures by Golov in view of Yamada in view of Chou in view of De Ambroggi in view Brailovskiy in view of Gieseke to include disclosures by Morabad since they both teach data storage, wherein Morabad is directed towards operation of storage device providing reliability and continuity (para. 2-3, 26). Therefore, it would be applying a known technique (NVMe controller writing data to a location identified by an LBA in a namespace) to a known device (device controlled by a system controller utilizing a memory controller for writing image files to nonvolatile memory and comprising respective regions corresponding to respective namespaces) ready for improvement to yield predictable results (device including an NVME controller configured to write data to a specified region of a non-volatile memory identified by an LBA and a namespace to allow for improved referencing of write locations). (MPEP 2143) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS KIM whose telephone number is (571)272-8093. The examiner can normally be reached Monday - Friday: 7:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.Y.K./Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135 Application/Control Number: 19/087,368 Page 2 Art Unit: 2135 Application/Control Number: 19/087,368 Page 3 Art Unit: 2135 Application/Control Number: 19/087,368 Page 4 Art Unit: 2135 Application/Control Number: 19/087,368 Page 5 Art Unit: 2135 Application/Control Number: 19/087,368 Page 6 Art Unit: 2135 Application/Control Number: 19/087,368 Page 7 Art Unit: 2135 Application/Control Number: 19/087,368 Page 8 Art Unit: 2135 Application/Control Number: 19/087,368 Page 9 Art Unit: 2135 Application/Control Number: 19/087,368 Page 10 Art Unit: 2135 Application/Control Number: 19/087,368 Page 11 Art Unit: 2135 Application/Control Number: 19/087,368 Page 12 Art Unit: 2135 Application/Control Number: 19/087,368 Page 13 Art Unit: 2135 Application/Control Number: 19/087,368 Page 14 Art Unit: 2135 Application/Control Number: 19/087,368 Page 15 Art Unit: 2135 Application/Control Number: 19/087,368 Page 16 Art Unit: 2135 Application/Control Number: 19/087,368 Page 17 Art Unit: 2135 Application/Control Number: 19/087,368 Page 18 Art Unit: 2135 Application/Control Number: 19/087,368 Page 19 Art Unit: 2135 Application/Control Number: 19/087,368 Page 20 Art Unit: 2135 Application/Control Number: 19/087,368 Page 21 Art Unit: 2135 Application/Control Number: 19/087,368 Page 22 Art Unit: 2135 Application/Control Number: 19/087,368 Page 23 Art Unit: 2135 Application/Control Number: 19/087,368 Page 24 Art Unit: 2135 Application/Control Number: 19/087,368 Page 25 Art Unit: 2135 Application/Control Number: 19/087,368 Page 26 Art Unit: 2135 Application/Control Number: 19/087,368 Page 27 Art Unit: 2135 Application/Control Number: 19/087,368 Page 28 Art Unit: 2135 Application/Control Number: 19/087,368 Page 29 Art Unit: 2135 Application/Control Number: 19/087,368 Page 30 Art Unit: 2135 Application/Control Number: 19/087,368 Page 31 Art Unit: 2135 Application/Control Number: 19/087,368 Page 32 Art Unit: 2135 Application/Control Number: 19/087,368 Page 33 Art Unit: 2135 Application/Control Number: 19/087,368 Page 34 Art Unit: 2135 Application/Control Number: 19/087,368 Page 35 Art Unit: 2135 Application/Control Number: 19/087,368 Page 36 Art Unit: 2135 Application/Control Number: 19/087,368 Page 37 Art Unit: 2135 Application/Control Number: 19/087,368 Page 38 Art Unit: 2135 Application/Control Number: 19/087,368 Page 39 Art Unit: 2135 Application/Control Number: 19/087,368 Page 40 Art Unit: 2135 Application/Control Number: 19/087,368 Page 41 Art Unit: 2135 Application/Control Number: 19/087,368 Page 42 Art Unit: 2135 Application/Control Number: 19/087,368 Page 43 Art Unit: 2135 Application/Control Number: 19/087,368 Page 44 Art Unit: 2135 Application/Control Number: 19/087,368 Page 45 Art Unit: 2135
Prosecution Insights