Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d), However, some of the certified copies of the priority documents have not been received.
Claims 1-20 are present for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on May 10, 2024. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0061865 application as required by 37 CFR 1.55.
Claim Objections
Claim 9 is objected to because of the following informalities:
Regarding claim 9: “first correction” in line 4 should read “the first correction.”
Appropriate correction is required.
Drawings
The drawings are objected to because of the following informalities:
Regarding FIG. 5: Element 304 “Clock Divier” should read “Clock Divider.”
Regarding FIG. 7: Element 354 “Clock Divier” should read “Clock Divider.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 11-12, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20140002155 A1) in view of Kwak (US 20070086267 A1).
Regarding claims 1, 11-12, and 20: Park discloses a Delay locked loop with a loop-embedded duty cycle corrector (FIG. 3), comprising: at least one memory device (DLL is widely used in a semiconductor memory device not shown, col. 1 ll. 28-31); a delay locked loop (DLL) (DDL, FIG. 3) configured to output a first correction value (control codes, par. 11) corresponding to a single cycle of a clock (period Tref of input clock RefCLK, par. 39); and a duty correction circuit configured to divide the clock in half (RefCLK into Divide-by-two circuit 210, FIG. 3), delay a divided clock (div2, FIG. 3) by a delay value corresponding to a half cycle of the clock (delay time of hfCLK is one-half of the period Tref (0.5*Tref), par. 37-38) to generate a delayed clock (hfCLK, FIG. 3), and generate an adjusted clock (FbCLK, par. 34-37, FIG. 3) having a duty ratio of 5:5 (FbCLK corrected to 50% duty cycle, par. 34) based on the divided clock (div2 into delay circuit 400, FIG. 3) and the delayed clock (DCC_out, relating to hfCLK, into delay circuit 400, par. 35, FIG. 3), wherein the delay value is adjusted or changed based on the first correction value (fbCLK adjusted by delay information of control codes, par. 44, FIG. 3).
Park does not disclose a controller coupled to the at least one memory device and configured to adjust a duty ratio of a clock to generate an adjusted clock when power is supplied and perform a read or write training based on the adjusted clock.
Kwak does disclose a clock generator having a delay locked loop and duty cycle correction circuit (FIG. 3), comprising: a controller (memory controller par. 41) coupled to the at least one memory device (memory device 900, FIG. 9) and perform a read or write training based on the adjusted clock (data read and write operations, par 43-44).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Park with the controller configuration of Kwak to allow the system to perform the data read and write operations based on the clocks like the claimed invention.
Regarding claims 3 and 14: Park does not disclose the semiconductor device, wherein the duty correction circuit comprises a divider configured to select one of a rising edge and a falling edge of the clock such that an output value of the divider transitions from a logic high level to a logic low level or from the logic low level to the logic high level based on a selected edge.
Kwak does disclose Kwak does disclose a clock generator having a delay locked loop and duty cycle correction circuit (FIG. 3), wherein the duty correction circuit comprises a divider (divider circuits 324 and 328, FIG. 2) configured to select one of a rising edge (rising edge of clock rCLK, FIG. 3) and a falling edge (falling edge of fCLK, FIG. 3) of the clock such that an output value of the divider transitions from a logic high level to a logic low level (output C goes from high to low, FIG. 3) or from the logic low level to the logic high level (output ! goes from low to high, FIG. 3) based on a selected edge.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Park with the configuration of Kwak to allow the system to perform the respective clock transition based on the selected rising or falling edge like the claimed invention.
Claim(s) 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20140002155 A1) in view of Kwak (US 20070086267 A1), in further view of Kumata (US 20070194823 A1).
Regarding claims 2 and 13: Park does not disclose the semiconductor device, wherein the delay locked loop is configured to detect a delay of the clock within the semiconductor device based on at least one of changes in an operational environment of the semiconductor device, including power supply and temperature, and changes in a manufacturing process, and to output the first correction value corresponding to the single cycle of the clock.
Kumata does disclose a digital DLL circuit (FIG. 2), wherein the delay locked loop is configured to detect a delay of the clock within the semiconductor device based on at least one of changes in an operational environment of the semiconductor device, including power supply and temperature, and changes in a manufacturing process (DLL circuit 10 detects delay due to variation in the supply voltage, temperature and process at the time of the fabrication of the LSI, par. 31, FIG. 2), and to output the first correction value corresponding to the single cycle of the clock (gate delay correction value GDCV, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Park and Kwak with the clock configuration of Kumata to have the system detect and perform operations based on the delay from the internal and external changes like the claimed invention.
Claim(s) 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20140002155 A1) in view of Kwak (US 20070086267 A1), in further view of Wada et al. (US 5764092 A).
Regarding claims 4 and 15: Park does not disclose the semiconductor, wherein the duty correction circuit comprises a first delay unit comprising N number of delay elements, where N is a positive integer, wherein each of the delay elements has a delay value corresponding to 1/N of the single cycle of the clock, and wherein the first delay unit is configured to delay the divided clock by a delay element selected from among the N number of delay elements based on a half of the first correction value.
Wada does disclose a delay clock generator, wherein the duty correction circuit comprises a first delay unit (delay clock, FIG. 3) comprising N number of delay elements (first to nth delay circuits, FIG. 3), where N is a positive integer (n: integer not less than 2, col. 2 ll. 14), wherein each of the delay elements has a delay value corresponding to 1/N of the single cycle of the clock (delay is 1/n of the basic clock period, col. 3 ll. 53-55), and wherein the first delay unit is configured to delay the divided clock by a delay element selected from among the N number of delay elements based on a half of the first correction value (nth delay control value from delay control circuit, col. 3 ll.60-63, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Park and Kwak with the delay configuration of Wada to allow the system to have the relationship between the number of delay elements and delay value as well as the control of the delay control value like the claimed invention.
Allowable Subject Matter
Claims 5-10 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: the structure of the duty correction circuit comprising a first inverter configured to invert the output divided clock and transfer an inverted and divided clock to the first delay unit as in claims 5 and 16; the structure of the duty correction circuit comprises: a first logic gate configured to perform an exclusive OR (XOR) operation on the divided clock, and the delayed clock, a second inverter configured to invert an output of the first logic gate, and a multiplexer configured to selectively output one of the output of the first logic gate and an output of the second inverter as in claims 7 and 18; and a fixed value filter between the delayed locked loop and the duty correction circuit configured to calculate an average value for first correction values continuously output from the delay locked loop (DLL) and transmit the average value to the first delay unit as in claims 9 and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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