DETAILED ACTION
This action is in response to communications: Preliminary-Amendment filed May 30, 2025.
Claims 1, 2, 6, 8, and 21-28 are pending in this case. Claims 1, 2, 6, and 8 have been newly amended. Claims 3-5, 7, and 9-20 have been newly cancelled. Claims 21-28 have been newly added. This action is made Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 2, 2025 and June 17, 2025 were filed after the filing date of the application on March 24, 2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on March 24, 2025. These drawings are accepted.
Claim Objections
Claims 6, 23, and 27 are objected to because of the following informalities:
Claims 6, 23, and 27 are dependent upon independent claims 1, 21, and 25, respectively, and similarly recite, “…wherein the selecting is further based on…” where independent claims 1, 21, and 25 do not have proper antecedent basis for “the selecting” but dependent claims 2, 22, 26 have proper antecedent basis. Therefore, it is considered claims 6, 23, and 27 depends upon claims 2, 22, and 26, respectively.
Claim 6, 23, and 27 similarly recite, “…whether a complier allows…” but should recite, “…whether a compiler allows…”
Appropriate correction is required.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 6, 8, and 21-28 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 9, 10, 14-17, and 20 of U.S. Patent No. 12,288,284. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application#19/087,823
1
2
6
8
21
22
23
24
U.S. Patent #12,288,284
16
16 & 17
20
16
16
16 & 17
20
16
Present Application#19/087,823
25
26
27
28
U.S. Patent #12,288,284
9 or 16
9 & 10
14 & 15
16
Present Application #19/087,823 Claim 1
U.S. Patent #12,288,284 Claim 16
An apparatus comprising:
A system comprising:
processing circuitry to:
one or more processors including a graphics processor, the one or more processors including one or more processing resources;
a memory for storage of data;
a texture sampler coupled with a texture cache;
a data port coupled with a data port cache; and
load a message include a texture load; and route the texture load to a destination, wherein the destination includes a texture sampler or a data port.
a message router to route a texture load from the one or more processing resources to a destination, wherein the destination may be either the texture sampler or the data port;
wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on:
support by the data port for a format of a memory surface for the texture load; and
a utilization metric for the data port representing a level of availability of the data port.
Claim 1 of the present application differs from claim 16 of the patent application in that claim 1 of the present application is broader in scope than claim 16 of the patent application, thus encompasses that of the patent application.
Present Application #19/087,823 Claim 2
U.S. Patent #12,288,284 Claims 16 and 17
The apparatus of claim 1, wherein
A system comprising…
the processing circuitry is further to select the destination for the texture load based on one or more of support for a format of a memory surface for the texture load or a utilization metric for the data port representing availability of a data port,
…wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on: support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing a level of availability of the data port (claim 16)...
wherein to select includes to determine whether the data port is authorized as the destination.
…wherein selection of the destination includes the arbitration circuitry determining that the data port is not authorized as the destination unless both the format for the memory surface for the texture message is supported by the data port and the utilization metric is below a threshold for capacity of the data port (claim 17).
Present Application #19/087,823 Claim 6
U.S. Patent #12,288,284 Claim 20
The apparatus of claim 1, wherein
The system of claim 16, wherein
the selecting is further based on a hint received from a shader
the arbitration circuitry is to further base selection of the destination on one or more of: a hint received from a shader;
or one or more of whether a complier allows routing of the texture load to the data port or whether a driver allows routing of the texture load to the data port.
whether a compiler allows routing of the texture load to the data port; or whether a driver allows routing of the texture load to the data port.
Present Application #19/087,823 Claim 8
U.S. Patent #12,288,284 Claim 16
The apparatus of claim 1, wherein
A system comprising:
the processing circuitry is coupled to a memory, the processing circuitry comprising one or more of graphics processing circuitry or application processing circuitry.
one or more processors including a graphics processor, the one or more processors including one or more processing resources; a memory for storage of data…
Present Application #19/087,823 Claim 21
U.S. Patent #12,288,284 Claim 16
A system comprising:
one or more processors including a graphics processor, the one or more processors including one or more processing resources;
a memory for storage of data;
a texture sampler coupled with a texture cache;
a data port coupled with a data port cache; and
A method comprising:
loading, by a computing device, a message including a texture load; and routing the texture load to a destination, wherein the destination includes a texture sampler or a data port.
a message router to route a texture load from the one or more processing resources to a destination, wherein the destination may be either the texture sampler or the data port;
wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on:
support by the data port for a format of a memory surface for the texture load; and
a utilization metric for the data port representing a level of availability of the data port.
Claim 21 of the present application differs from claim 16 of the patent application in that claim 21 of the present application is broader in scope than claim 16 of the patent application, thus encompasses that of the patent application.
Present Application #19/087,823 Claim 22
U.S. Patent #12,288,284 Claims 16 and 17
The method of claim 21, further comprising
A system comprising…
selecting the destination for the texture load based on one or more of support for a format of a memory surface for the texture load or a utilization metric for the data port representing availability of a data port,
…wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on: support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing a level of availability of the data port (claim 16)...
wherein selecting includes determining whether the data port is authorized as the destination.
…wherein selection of the destination includes the arbitration circuitry determining that the data port is not authorized as the destination unless both the format for the memory surface for the texture message is supported by the data port and the utilization metric is below a threshold for capacity of the data port (claim 17).
Present Application #19/087,823 Claim 23
U.S. Patent #12,288,284 Claim 20
The method of claim 21, wherein
The system of claim 16, wherein
the selecting is further based on a hint received from a shader or
the arbitration circuitry is to further base selection of the destination on one or more of: a hint received from a shader;
one or more of whether a complier allows routing of the texture load to the data port or whether a driver allows routing of the texture load to the data port.
whether a compiler allows routing of the texture load to the data port; or whether a driver allows routing of the texture load to the data port.
Present Application #19/087,823 Claim 24
U.S. Patent #12,288,284 Claim 16
The method of claim 21, wherein
A system comprising:
the computing device comprises processing circuitry coupled to a memory, the processing circuitry having one or more of graphics processing circuitry or application processing circuitry.
one or more processors including a graphics processor, the one or more processors including one or more processing resources; a memory for storage of data…
Present Application #19/087,823 Claim 25
U.S. Patent #12,288,284 Claim 9
At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
loading a message including a texture load; and
receiving a message including a texture load at a message router for a graphics processor;
determining support by a data port for the graphics processor for a format for a memory surface for the texture load;
determining a level of availability of the data port; and
routing the texture load to a destination, wherein the destination includes a texture sampler or a data port.
selecting either the data port or a texture sampler as a destination for the texture load based at least on the determined support for the format of the memory surface for the texture load and on the determined level of availability for the data port.
Claim 25 of the present application differs from claim 9 of the patent application in that claim 25 of the present application is broader in scope than claim 9 of the patent application, thus encompasses that of the patent application.
NOTE: Claim 25 of the present application is similar in scope to claim 1 of the present application, thus may also be rejected against claim 16 of the patent application as outlined above.
Present Application #19/087,823 Claim 26
U.S. Patent #12,288,284 Claims 9 and 10
The computer-readable medium of claim 25, wherein
One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising…
the operations further comprise selecting the destination for the texture load based on one or more of support for a format of a memory surface for the texture load or a utilization metric for the data port representing availability of a data port,
…selecting either the data port or a texture sampler as a destination for the texture load based at least on the determined support for the format of the memory surface for the texture load and on the determined level of availability for the data port (claim 9)…
wherein selecting includes determining whether the data port is authorized as the destination.
…wherein selection of the destination includes determining that the data port is not authorized as the destination unless both the format for the memory surface for the texture message is supported by the data port and the level of availability meets a threshold for capacity of the data port (claim 10).
Present Application #19/087,823 Claim 27
U.S. Patent #12,288,284 Claims 14 and 15
The computer-readable medium of claim 25, wherein
The storage mediums of claim 9, wherein
the selecting is further based on a hint received from a shader or
selection of the destination for the texture load is further based on a hint received from a shader (claim 14)...
one or more of whether a complier allows routing of the texture load to the data port or whether a driver allows routing of the texture load to the data port.
… wherein selection of the destination for the texture load is further based on one or more of: whether a compiler allows routing of the texture load to the data port; or whether a driver allows routing of the texture load to the data port (claim 15).
Present Application #19/087,823 Claim 24
U.S. Patent #12,288,284 Claim 16
The computer-readable medium of claim 25, wherein
A system comprising:
the computing device comprises processing circuitry coupled to a memory, the processing circuitry having one or more of graphics processing circuitry or application processing circuitry.
one or more processors including a graphics processor, the one or more processors including one or more processing resources; a memory for storage of data…
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 21, 24, 25, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sprangle (US 8,933,946) in view of HEINRICH et al. (US 2015/0084975).
As to claim 1, Sprangle discloses an apparatus comprising (Figure 2, hardware 200 which is further implemented in system of Figure 1): processing circuitry (processor 105 comprising processing elements (PE), 106, 107, further comprising a plurality of cores, e.g. core 201) to: load a message including a texture load (Figure 3, step 300, column 6, lines 30-37 notes detecting a texture sample operation for a pixel, step 305, column 6, lines 38-49 notes inserting a pre-fetch texture sample operation, the texture sample operation is replaced by the pre-fetch texture operation in compiled binary code, the pre-fetch texture sample operation, e.g. pre-fetch operation 205, may include texture sample information such as coordinates of the pixel (Coord 206) and a destination address for the texel (DA 207), which may include a virtual address or pointer to a virtual address, step 310, column 6, lines 50-52 further notes inserting a load operation in the application code); and route the texture load to a destination, wherein the destination includes a texture sampler (Figure 2, column 4, lines 27 thru column 5, lines 5 notes in response to core 201 executing pre-fetch operation 205, core 201 is to delegate texture sampling of a pixel to hardware sampling unit 210, e.g. by providing coordinates of the pixel, e.g. coordinates (Coord) 206, and a destination address, e.g. destination address (DA) 207, to texture sampling unit 210, where texture sampling unit 210 performs texture sampling for the referenced pixel to obtain a textured pixel, e.g. texel, then the texel is provided to the destination address, e.g. DA 207 references destination as cache line 216 in cache 215, and column 5, lines 53-62 further notes a normal load operation may be executed to load the texel from the destination address, e.g. via load logic 220 for further processing, thus may be considered the destination includes a texture sampler, texture sampling unit 210).
As noted above, Sprangle discloses its processing circuitry to route the texture load to a destination, wherein the destination includes a texture sampler, but do not explicitly disclose “…wherein the destination includes a texture sampler or a data port.”
HEINRICH et al. also disclose an apparatus (Figure 1, computer system 100) comprising: processing circuitry (parallel processing unit (PPU) 202 of Figure 2 implemented in parallel processing subsystem 112) to: load a message including a texture load (e.g. a memory access request representing a texture data access operation, further including a load operation); and route the texture load to a destination, wherein the destination includes a texture sampler or a data port (e.g. route memory access request representing a texture data access operation to one of level-of-detail (LOD) unit 406 then sampling control and address unit 408 or to bypass multiplexer 409 then to other units)(Figure 4, associated text, e.g. [0051] notes TEXIN unit 402 to process memory access requests, or operations, received from SM 310, memory access requests may represent a texture data access operation or a generic, non-texture memory access operation, where [0055] further notes in the case when the memory access request represents a texture data access operation, the TEXIN unit 402 configures the texture processing pipeline to perform a texture data access operation and routes the memory access request to the LOD unit 406, [0058] notes the sampling control and address unit 408 is further configured to perform various address computations based on the coordinates within the memory access request, e.g. the texture data access operation, [0059] notes the bypass multiplexer 409 provides a route around the LOD unit 406 and the sampling control and address unit 408 for operations that do not need these two units for performing a particular operation, e.g. as an example, a texture operation could use the LOD unit 406 and the sampling control and address unit 408 to access a level of detail within the texture cache, accordingly, the bypass multiplexer 409 would be configured to select input 430 to route the output of the sampling control and address unit 408 to the tag unit 410, as another example, a load operation could be completed without using the functions of the LOD unit 406 and the sampling control and address unit 408, where the bypass multiplexer 409 would be configured to select input 432 to route the output of the TEXIN unit 402 to the tag unit 410, where the bypass multiplexer 409 may bypass more or fewer units than shown). It is noted that the memory access request, e.g. texture data access operation may include a load operation, where it may be determined whether certain operations may or may not need to be performed, thus determines one of multiple destinations where to route the memory access request, e.g. texture access operation.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Sprangle’s system and method of routing a texture sample operation, including a pre-fetch (load) operation, with HEINRICH et al.’s method of determining where to route a texture data access operation, including a load operation, to one of multiple destinations as certain operations may or may not need to be performed using the texture data access operation, thus enhancing the system by avoiding unnecessary processing (see [0059] of HEINRICH et al.).
As to claim 8, Sprangle modified with HEINRICH et al. disclose the processing circuitry is coupled to a memory (Sprangle, processor 105 coupled to memory 130; modified with HEINRICH, PPU 202 coupled to at least PP memory 204), the processing circuitry comprising one or more of graphics processing circuitry or application processing circuitry (Sprangle, column 2, lines 62 thru column 3, lines 3 notes processor 105 may include a microprocessor, an embedded processor, a multi-core processor, a multi-threaded processor, a graphics processor, a media processor, or a signal processor, additionally, processor 105 processes application code 131 of memory 130, thus may be considered an application processing circuitry; modified with HEINRICH, [0029] notes PPU 202 comprises a graphics processing unit (GPU)).
As to claim 21, Sprangle modified with HEINRICH et al. disclose a method comprising the operations as performed by the processing circuitry of the apparatus of claim 1. Please see the rejection and rationale of claim 1.
Claim 24 is similar in scope to claim 8, and is therefore rejected under similar rationale.
As to claim 25, Sprangle modified with HEINRICH et al. disclose at least one computer-readable medium (Sprangle, Figure 1, memory 130; modified with HEINRICH, Figure 1, system memory 103) having stored thereon instructions (Sprangle, e.g. at least application code 131; modified with HEINRICH, device driver 103) which, when executed, cause a computing device (Sprangle, e.g. executed by processor 105 (further including components of Figure 2) of computing system 100; modified with HEINRICH, computer system 100) to perform operations as performed by the processing circuitry (Sprangle, column 2, lines 27-41; modified with HEINRICH, parallel processing unit (PPU) 202 of Figure 2 implemented in parallel processing subsystem 112) of the apparatus of claim 1. Please see the rejection and rationale of claim 1.
Claim 28 is similar in scope to claim 8, and is therefore rejected under similar rationale.
Allowable Subject Matter
Claims 2, 6, 22, 23, 26, and 27 would be allowable if the Double Patenting rejection may be overcome AND if rewritten in independent form including ALL of the limitations of the base claim AND any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claims 2, 22, and 26, the prior art of record fails to teach or suggest the limitations of the claims as recited.
Regarding dependent claims 6, 23, and 27, as noted in the claim objection above, it is considered these claims depend upon claims 6, 23, and 27, respectively, thus are indicated allowable for depending upon indicated allowable claims, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lindholm et al. (US 8,624,910) disclose a system and method of indexed texture headers and samplers, the method includes determining if a texture operation specifies an index associated with a texture sampler and routing accordingly.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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