DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 7-10, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The Examiner is unclear as to what the limitation “externally-supplied” signal means as it is used in claims 1-2, 7-10, and 20. The claims are not clear in the indication that there is any structural means that supply these signals. Therefore, the Examiner will examine the claims using the broadest and most reasonable interpretation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 12, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tokuda, Takamitsu et al. (2023/0311486 A1) (hereinafter Tokuda, Takamitsu et al.).
Regarding Claim 1, Tokuda, Takamitsu et al. teaches a print element board (200, Fig. 3) [Paragraphs 0032-0036] comprising: a plurality of first print elements (301, Figs. 6A-6B) [Paragraphs 0037-0042]; a plurality of second print elements (301) [Paragraphs 0037-0042]; a plurality of first drive elements (not shown in Figures) configured to drive the plurality of first print elements (301) [Paragraphs 0037-0047]; a plurality of second drive elements (not shown in Figures) configured to drive the plurality of second print elements (301) [Paragraphs 0037-0047]; a drive signal generation circuit (411, Fig. 7) configured to generate a first drive signal (not shown in Figures) and a second drive signal (not shown in Figures) [Paragraphs 0043-0047]; and a drive signal selection circuit (412, Fig. 7) configured to select both or one of the first drive signal (not shown in Figures) and the second drive signal (not shown in Figures) based on an externally-supplied operation switching signal (not shown in Figures), wherein at least one of the first drive elements (not shown in Figures) and at least one of the second drive elements (not shown in Figures) operate based on the drive signal selected by the drive signal selection circuit (412) [Paragraphs 0043-0055].
Regarding Claim 12, Tokuda, Takamitsu et al. teaches the print element board (200), further comprising: a plurality of first control circuits (408, Fig. 7) configured to cause the at least one of the first drive elements (not shown in Figures) to operate based on a selection signal selected by the drive signal selection circuit (412) for the at least one of the first drive elements (not shown in Figures) [Paragraphs 0043-0055]; and a plurality of second control circuits (not shown in Figures) configured to cause the at least one of the second drive elements (not shown in Figures) to operate based on a selection signal selected by the drive signal selection circuit (412) for the at least one of the second drive elements (not shown in Figures) [Paragraphs 0043-0055].
Regarding Claim 19, Tokuda, Takamitsu et al. teaches a print head (101, Figs. 1 and 3) using the print element board (200, Fig. 3) [Paragraphs 0032-0036], the print head (101) comprising a plurality of ejection ports (not shown in Figures) configured to eject liquid [Paragraph 0031, see also Figs. 1 and 3].
Regarding Claim 20, Tokuda, Takamitsu et al. teaches A printing apparatus (see Fig. 1) configured to perform printing on a print medium (105, Fig. 1) by using a print head (101, Figs. 1 and 3) using a print element board (200, Fig. 3) including a plurality of first print elements (301, Figs. 6A-6B), a plurality of second print elements (301), a plurality of first drive elements (not shown in Figures) configured to drive the plurality of first print elements (301), a plurality of second drive elements (not shown in Figures) configured to drive the plurality of second print elements (301) [Paragraphs 0027-0047], a drive signal generation circuit (411, Fig. 7) configured to generate a first drive signal (not shown in Figures) and a second drive signal (not shown in Figures), and a drive signal selection circuit (412, Fig. 7) configured to select both or one of the first drive signal (not shown in Figures) and the second drive signal (not shown in Figures) based on an externally-supplied operation switching signal (not shown in Figures), wherein at least one of the first drive elements (not shown in Figures) and at least one of the second drive elements (not shown in Figures) operate based on the drive signal selected by the drive signal selection circuit (412) [Paragraphs 0043-0055], the print head (101) includes a plurality of ejection ports (not shown in Figures) configured to eject liquid, the liquid is ink, the print head (101) is used as a print head (101) configured to eject the ink, and the ink is ejected from the ejection ports (not shown in Figures) by driving the plurality of first print elements (301) and the plurality of second print elements (301) [Paragraphs 0027-0042].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokuda, Takamitsu et al. (2023/0311486 A1) (Tokuda, Takamitsu et al.) in view of Kasai et al. (2020/0369025 A1) (hereinafter Kasai et al.).
Regarding Claim 2, Tokuda, Takamitsu et al. teaches the print element board (200, Fig. 1) [Paragraphs 0027-0047].
Tokuda, Takamitsu et al. fails to teach, further comprising a data expansion circuit configured to expand an externally-supplied serial signal based on an externally- supplied clock signal and an externally-supplied latch signal, wherein the at least one of the first drive elements is a drive element selected from among the plurality of first print elements based on a first element selection signal expanded by the data expansion circuit, the at least one of the second drive elements is a drive element selected from among the plurality of second print elements based on a second element selection signal expanded by the data expansion circuit, and the signals expanded by the data expansion circuit are updated every block period.
Kasai et al. teaches further comprising a data expansion circuit configured to expand an externally-supplied serial signal based on an externally- supplied clock signal and an externally-supplied latch signal, wherein the at least one of the first drive elements is a drive element selected from among the plurality of first print elements based on a first element selection signal expanded by the data expansion circuit, the at least one of the second drive elements is a drive element selected from among the plurality of second print elements based on a second element selection signal expanded by the data expansion circuit, and the signals expanded by the data expansion circuit are updated every block period [Paragraphs 0042-0053].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a data expansion circuit configured to expand an externally-supplied serial signal based on an externally- supplied clock signal and an externally-supplied latch signal, wherein the at least one of the first drive elements is a drive element selected from among the plurality of first print elements based on a first element selection signal expanded by the data expansion circuit, the at least one of the second drive elements is a drive element selected from among the plurality of second print elements based on a second element selection signal expanded by the data expansion circuit, and the signals expanded by the data expansion circuit are updated every block period as taught by Tokuda, Takamitsu et al. as modified by Kasai et al. for the purposes of reducing the current peak along with driving when using a plurality of drive signals [Kasai et al., Paragraph 0011].
Allowable Subject Matter
Claims 3-6 and 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the allowance of claims 3-4 is the inclusion of the limitation of a print element board that includes two cases in which the drive signal selection circuit selects at least one of a first and second drive signals for at least one of the first drive elements and selects the other one of the first and second drive signals for at least one of a second drive elements when an operation switching signal is a first value and the drive selection circuit selects one or the other one of the first and second drive signals in common for at least one of the first and second drive elements when the operation switching signal is a second value. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 5-6 is the inclusion of the limitation of a print element board that includes two block periods in which the drive signal selection circuit selects at least one of a first and second drive signals for at least one of the first drive elements and selects the other one of the first and second drive signals for at least one of a second drive elements when an operation switching signal is a first value and the drive selection circuit selects one or the other one of the first and second drive signals for at least one of the first and second drive elements when the operation switching signal is a third value. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 11 is the inclusion of the limitation of a print element board that includes a delay element causes a drive signal that drive signal selection circuit selects for at least one of a first drive elements that supplies a signal to separate first drive elements selectable by the first element selection signal with separate delay times; and a delay element causes a drive signal that drive signal selection circuit selects for at least one of a second drive elements that supplies a signal to separate second drive elements selectable by the second element selection signal with separate delay times. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 13 is the inclusion of the limitation of a print element board that includes a delay element causes a delay to a drive signal that a drive signal selection circuit selects for at least one of a first drive elements that supplies a signal to a plurality of first control circuits; and a delay element causes a delay to a drive signal that the drive signal selection circuit selects for at least one of a second drive elements that supplies a signal to a plurality of second control circuits. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 14-16 is the inclusion of the limitation of a print element board that includes a first drive signal has a waveform that causes first drive elements or second drive elements to drive print elements corresponding to the first or second drive elements in a first portion of a block period and a second drive signal has a waveform that causes first drive elements or second drive elements to drive print elements corresponding to the first or second drive elements in a second portion of a block period, wherein the second portion is later than the first portion of the block period in terms of time. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 17 is the inclusion of the limitation of a print element board that includes wherein a drive signal generation circuit, a portion generates a first drive signal, and a portion generates a second drive signal are common, and the drive signal generation circuit generates the first and second drive signal on a basis of a common pattern designation signal. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
The primary reason for the allowance of claim(s) 18 is the inclusion of the limitation of a print element board that includes a first drive signal generation circuit generates a first drive signal on a basis of a first individual pattern designation signal; and a second drive signal generation circuit generates a second drive signal on a basis of a second individual pattern designation signal. It is these limitations found in the claims, as it is claimed in the combination, that has not been found, taught, or suggested by the prior art of record, which makes these claims allowable over the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA SOLOMON whose telephone number is (571)272-1701. The examiner can normally be reached Monday - Friday, 9:30am -6pm, EST.
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/LISA SOLOMON/Primary Examiner, Art Unit 2853
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