Prosecution Insights
Last updated: October 02, 2026
Application No. 19/088,352

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Mar 24, 2025
Priority
May 14, 2024 — JP 2024-078595
Examiner
THOMAS, LUCY M
Art Unit
Tech Center
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
1y 7m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
513 granted / 822 resolved
+2.4% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
39 currently pending
Career history
848
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
55.1%
+15.1% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
12.6%
-27.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 822 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Minagawa (US 2021/0296881, IDS Document). Regarding Claim 1, Minagawa discloses a semiconductor device (Figures 1, 14, 19-24) comprising: a semiconductor element having a switching element (comprising 2, Figure 1, 2a, Figure 14), a temperature detection section configured to detect a temperature of the switching element (comprising diode 8, Figures 1,14), and a current detection section configured to detect a current of the switching element (comprising sense voltage detection resistor 7 coupled to overcurrent detection terminal OC, Figures 1, 14); and a control circuit configured to control the semiconductor element (comprising 1, Figures 1, 14), wherein the control circuit has: a signal generation section (comprising 4, Figures 1-2,5-6, 9, 14) configured to generate a temperature variable signal varying according to a detection temperature detected by the temperature detection section using a temperature detection signal having information on the detection temperature (VF1); and an overcurrent detection section (comprising comparator 6, Figures 1, 14) configured to detect that a current flowing into the switching element is an overcurrent using a current detection signal having information on a detection current detected by the current detection section and the temperature variable signal output from the signal generation section (6 comparing the current detected at OC terminal by resistor 7 and the output VOC of 4 to output a detection signal to filter 13, Figures 1, 14, Paragraphs 67,73, 75). Regarding Claim 2, Minagawa discloses the semiconductor device according to Claim 1, wherein the signal generation section has: a first reference signal generation section configured to generate a first reference signal having a temperature-independent voltage (comprising VOCo, Figures 1, 14); and a temperature variable signal generation section (comprising 4, Figures 1, 14) configured to generate the temperature variable signal based on a difference between the first reference signal output from the first reference signal generation section and the temperature detection signal (4 outputting VOC based on VF2,VF1, VOCo inputs, Figures 1, 14). Regarding Claim 3, Minagawa discloses the semiconductor device according to Claim 2, wherein the temperature variable signal generation section has: a differential circuit configured to generate a differential signal between the first reference signal and the temperature detection signal (121 comparing VF2 and VF1 to output VOCa, Figures 2,5, see also Figures 6,9-10); and a level change circuit configured to change a signal level of the differential signal output from the differential circuit (131 comparing VOCa with VOCo to output VOC, Figures 2, 5, see also Figures 6,9-10). Regarding Claim 4, Minagawa discloses the semiconductor device according to Claim 1, wherein the overcurrent detection section has: a comparator configured to compare the temperature variable signal with the current detection signal (comparator 6 with current detection signal at OC terminal detected by sense resistor 7 and output VOC from 4, Figures 1, 14, Paragraphs 67, 73, 75). Regarding Claim 5, Minagawa discloses the semiconductor device according to Claim 4, wherein the overcurrent detection section is configured to detect that an overcurrent flows into the switching element when the comparator outputs a signal indicating that the current detection signal has a signal level higher than a signal level of the temperature variable signal (output of comparator 6 to filter 13, Figures 1, 14, Paragraphs 67,73, 75). Regarding Claim 8, Minagawa discloses the semiconductor device according to Claim 1, wherein the temperature detection section is provided in a semiconductor chip substrate where the semiconductor element is formed, in an insulating substrate where the semiconductor element is mounted, in a circuit board where the control circuit is mounted, inside a resin case where the semiconductor element and the control circuit are housed, or outside the resin case in contact with the resin case (Paragraph 68). Regarding Claim 9, Minagawa discloses the semiconductor device according to Claim 1, wherein the switching element is an insulated gate bipolar transistor or a metal-oxide-semiconductor field- effect transistor (IGBT transistor 2, Figures 1, 14, Paragraph 67, “….an IGBT is used as the switching element 2…”). Regarding Claim 10, Minagawa discloses the semiconductor device according to Claim 1, wherein the temperature detection section is a temperature-dependent diode (temperature detection diode 8, Figures 1, 14, Paragraph 67). Regarding Claim 11, Minagawa discloses the semiconductor device according to Claim 2, wherein the overcurrent detection section has: a comparator configured to compare the temperature variable signal with the current detection signal (comparator 6 with current detection signal at OC terminal detected by sense resistor 7 and output VOC from 4, Figures 1, 14, Paragraphs 67, 73, 75). Regarding Claim 12, Minagawa discloses the semiconductor device according to Claim 11, wherein the overcurrent detection section is configured to detect that an overcurrent flows into the switching element when the comparator outputs a signal indicating that the current detection signal has a signal level higher than a signal level of the temperature variable signal (output of comparator 6 to filter 13, Figures 1, 14, Paragraphs 67,73, 75). Regarding Claim 13, Minagawa discloses the semiconductor device according to Claim 3, wherein the overcurrent detection section has: a comparator configured to compare the temperature variable signal with the current detection signal (comparator 6 with current detection signal at OC terminal detected by sense resistor 7 and output VOC from 4, Figures 1, 14). Regarding Claim 14, Minagawa discloses the semiconductor device according to Claim 13, wherein the overcurrent detection section is configured to detect that an overcurrent flows into the switching element when the comparator outputs a signal indicating that the current detection signal has a signal level higher than a signal level of the temperature variable signal (comparator 6 with current detection signal at OC terminal detected by sense resistor 7 and output VOC from 4, Figures 1, 14). Allowable Subject Matter Claims 6-7, 15-16, 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 6, Minagawa discloses the semiconductor device according to Claim 1, wherein the overcurrent detection section receives the temperature variable signal as a second reference signal (VOC signal output received from 4, Figures 1, 14); and a comparator configured to compare the second reference signal output from the second reference signal generation circuit with the current detection signal (comparator 6 compares VOC signal with current detection from OC terminal, Figures 1, 14). Minagawa discloses in prior art Figure 13, the overcurrent detection section has a second reference signal generation circuit configured to generate a second reference signal (comprising VOC, 5a, Figure 13). Minagawa does not disclose the overcurrent detection section has: a second reference signal generation circuit configured to generate the second reference signal having a signal level varying according to a signal level of the temperature variable signal, in combination with the other recited elements of Claim 6, and would be allowable if rewritten in independent for including all limitations of the base claim and any intervening claims. Claim 7 depend from Claim 6 and is objected due to dependency to an objected claim. Claims 15 and 17 recite the same limitations as Claim 6, except for the dependency to Claims 2, 3 respectively. Therefore, Claims 15, 17 are objected to similarly to Claim 6. Claims 16, 18 depend from objected claims 15, 17 respectively. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kumagai (US 2005/0099751) discloses in Figures 1-2, a semiconductor device comprising: a semiconductor element having a switching element 10, a temperature detection section 6, 34 configured to detect a temperature of the switching element, and a current detection section 2a, 32 configured to detect a current of the switching element; and a control circuit 35, 31 configured to control the semiconductor element; Akahane (US 2015/0309090) discloses in Figure 1, a semiconductor device comprising: a semiconductor element having a switching element Q, a current detection section 3 configured to detect a current of the switching element; an overcurrent detection circuit 5 having a reference signal generating circuit, and a control circuit 2 configured to control the semiconductor element. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LUCY M THOMAS/Examiner, Art Unit 2838, 8/22/2026 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 24, 2025
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
80%
With Interview (+17.9%)
3y 1m (~1y 7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 822 resolved cases by this examiner. Grant probability derived from career allowance rate.

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