Prosecution Insights
Last updated: October 02, 2026
Application No. 19/088,392

DRIVER CIRCUIT

Non-Final OA §102§103
Filed
Mar 24, 2025
Priority
Apr 18, 2024 — JP 2024-067606
Examiner
CLARK, CHRISTOPHER JAY
Art Unit
Tech Center
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
574 granted / 757 resolved
+15.8% vs TC avg
Strong +23% interview lift
Without
With
+22.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
770
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 757 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 4, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al (6,595,194). In re Claim 1, Ito teaches a driver circuit as seen in Figure 1 comprising: a transistor (110) including a ground side electrode, a control electrode, and a power supply side electrode for an inductive load (20) to be connected thereto; a first resistor (R2) connected to the control electrode; a line connected to the first resistor (from 100in to R2); a second resistor (R1) provided between the line and a ground; a first diode (ZD3), including: a cathode connected to the line, and an anode, the first diode being connected in parallel with the second resistor; and a second diode (ZD1) including: a cathode connected to the line (via 150), and an anode for connecting to a capacitor (16), thereby receiving a voltage generated in the capacitor for driving the transistor. In re Claims 3 and 4, Ito teaches the driver circuit is configured with a semiconductor integrated circuit (100’, col 3 lines 31-34 and col 4 lines 37-52) and that both the diodes ZD1 and ZD3 are Zener diodes (col 3 lines 43-46 and lines 58-60). In re Claim 6, Ito teaches the inductive load is an ignition coil (col 3 lines 12-15) and the driver circuit is an igniter (col 2 lines 62-65). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al (6,595,194) in view of JP 7-16593 w/ reference made to the translation, hereinafter referred to as “JP ‘593”). In re Claim 2, Ito describes diode ZD1 as a Zener diode (col 3 lines 58-60), but does not specifically describe its forward voltage. JP ‘593 describes a Zener diode having a forward voltage of 0.6 V (see highlighted portion of translation). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the Zener diode ZD1 of Ito with a forward voltage of 0.6 V since JP ‘593 teaches that 0.6 V is a known forward voltage for a Zener diode. Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In re Claim 5, Ishii (9,719,479) teaches placing a third diode Ds in parallel with a first resistor R1 as seen in Figure 1 in order for fast turning off of the switch 21 (col 3 lines 49-54). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the diode Ds as taught by Ishii in parallel with the first resistor R2 of Ito in order to provide a fast turn off. However, neither Ito nor Ishii teach or suggest that the resistance value of the first resistor R2 being specifically larger than the resistance the second resistor R1 of Ito. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER JAY CLARK whose telephone number is (571)270-1427. The examiner can normally be reached Monday - Friday, 10:00am - 6:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER J CLARK/Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Mar 24, 2025
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 6m to grant Granted Sep 15, 2026
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2y 5m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.8%)
2y 9m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 757 resolved cases by this examiner. Grant probability derived from career allowance rate.

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