CTNF 19/088,654 CTNF 84745 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This action is in response to the application filed on 01/08/2019, in which claims 1-19 are presented for the examination. Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 04/04/2019 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS statement is being considered by the examiner. Drawings The drawings filed on 01/08/2019 are accepted by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 6-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khan et al. (US 2016/0378352, referred herein after Khan) in view of Srivastava et al. (US 2016/0172058, referred herein after Srivastava) . As per claim 1, Khan discloses a device comprising: a memory (Fig. 1, memory 114, [0018]); a logic circuit coupled to the memory (Fig. 1, Logic 160 coupled to memory 114, [0018]-[0019]); and a non-volatile memory coupled to the logic circuit (abstract, logic, coupled to non-volatile memory) ; wherein the compressed code indicates a number of padding bits for an uncompressed code associated with the defective area of the memory ([0074], the compressed data stored in non-volatile memory includes common meta information, which may comprise one or more padding bits. Padding bits are generally used to align the data structure to make it to standard size (ie uncompressed/full data size) according to memory architecture and required by the CPU); Khan does not disclose configurable to store a compressed code associated with a defective area of the memory; However, Srivastava discloses configurable to store a compressed code associated with a defective area of the memory (abstract, [0003], [0013], “ each memory system includes a memory module and an associated first repair register for receiving compressed memory repair data“, since the data associated with the defective area of the memory is not defined, applying BRI, the repair data is interpreted as data associated with a defective area of the memory as claimed); Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Srivastava’s method for handling repair data into Khan’s efficient solid state drive data compression method because one of the ordinary skill in the art would have been motivated to recover usable data, improve fault tolerance and reduce the storage waste. As per claim 2, Khan discloses device of claim 1, wherein the logic circuit is configurable to decompress the compressed code to generate the uncompressed code by concatenating the padding bits with a portion of the compressed code ([0074], the one or more padding bits are to pad the compressed data to a nearest indirection granularity boundary). As per claim 3, 12, Khan discloses the device of claim 2, wherein the logic circuit is configurable to: couple to memory chains; and (Fig. 1, logic circuit connected to memory 114, SSD 130) shift the uncompressed code to the memory chains ([0013], [0014], [0032], uncompressed data stored in memory). As per claim 4, 13, Srivastava discloses the device of claim 3, wherein the logic circuit is configurable to shift a clock signal to the memory chains after restoring the uncompressed code ([0013], [0018], shift operation is completed after restoring uncompressed repair data). As per claim 6, 15, Khan discloses the device of claim 1, wherein the logic circuit is configurable to perform a code check on the compressed code by at least identifying one or more bits in the compressed code ([0024], a compression token (which could be one or more bits) indicates whether a block has been compressed (or not)). As per claim 7, 16, Khan discloses the device of claim 1, wherein the logic circuit is configurable to determine correctness of the compressed code based on one or more bits in the compressed code ([0037], [0057], [0074], the compression token is to indicate whether a corresponding portion of data is compressed). As per claim 8, 17, Khan discloses the device of claim 7, wherein to determine the correctness of the compressed code, the logic circuit is configurable to use the one or more bits as a flag ([0037], [0057], [0074], the compression token (ie flag as claimed) is to indicate whether a corresponding portion of data is compressed). As per claim 9, 18, device of claim 1, wherein the logic circuit is configurable to determine a valid length of the compressed code using one or more bits in the compressed code ( [0074], the padding bits (padding bits determines valid length as claimed)). As per claim 10, 19, device of claim 9, wherein to determine the valid length of the compressed code, the logic circuit is configurable to use the one or more bits in the compressed code as a flag ([0037], [0057], [0074], presence of padding bits acts a flag as claimed). As per claim 11, 20, Khan discloses a method comprising: storing, by a logic circuit to a non-volatile memory coupled to the logic circuit, wherein the compressed code indicates a number of padding bits for an uncompressed code associated with the defective area of the memory (Fig. 3C, 3D, [0074], the compressed data stored in non-volatile memory includes common meta information, which may comprise one or more padding bits. Padding bits are generally used to align the data structure to make it to standard size (ie uncompressed/full data size) according to memory architecture and required by the CPU); and decompressing, by the logic circuit, the compressed code to generate the uncompressed code by concatenating the padding bits with a portion of the compressed code ([0013], [0074], a novel padding scheme which enables super scalar data decompression, the one or more padding bits are to pad the compressed data, [0028]-[0031] the intelligent nearest 512 B padding scheme for use in super scalar data decompression); Khan does not disclose a compressed code associated with a defective area of a memory; However, Srivastava discloses a compressed code associated with a defective area of a memory (abstract, [0003], [0013], “ each memory system includes a memory module and an associated first repair register for receiving compressed memory repair data“, since the data associated with the defective area of the memory is not defined, applying BRI, the repair data is interpreted as data associated with a defective area of the memory as claimed); Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Srivastava’s method for handling repair data into Khan’s efficient solid state drive data compression method because one of the ordinary skill in the art would have been motivated to recover usable data, improve fault tolerance and reduce the storage waste . 07-21-aia AIA Claim s 5, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Khan and Srivastava in view of Gorman et al. (US 2013/0031319, referred herein after Gorman) . As per claim 5, 14, neither Khan nor Srivastava specifically discloses the device of claim 3, wherein the logic circuit is configurable to pause operation of a controller while shifting the uncompressed code to the memory chains; However, Gorman discloses the logic circuit is configurable to pause operation of a controller while shifting the uncompressed code to the memory chains ([0030], [0033], data compression operation is halted); Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Gorman’s method for interleaving memory repair data compression and fuse programming operations into Khan’s efficient solid state drive data compression method and Srivastava’s method for handling repair data because one of the ordinary skill in the art would have been motivated to allow for more efficient memory usage and processing of data and reducing overall load on the controller . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form 892 . White teaches testing method for one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. Zorian teaches a system that generate an augmented repair signature to repair all of the defects detected in a first test of a memory as well as in a second test of the memory. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMINI B PATEL whose telephone number is (571)270-3902. The examiner can normally be reached on M-F 8-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAMINI B PATEL/Primary Examiner, Art Unit 2114 Application/Control Number: 19/088,654 Page 2 Art Unit: 2114 Application/Control Number: 19/088,654 Page 3 Art Unit: 2114 Application/Control Number: 19/088,654 Page 4 Art Unit: 2114 Application/Control Number: 19/088,654 Page 5 Art Unit: 2114 Application/Control Number: 19/088,654 Page 6 Art Unit: 2114 Application/Control Number: 19/088,654 Page 7 Art Unit: 2114 Application/Control Number: 19/088,654 Page 8 Art Unit: 2114
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