DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Applicant’s disclosure in paragraph [0000], p. 1 recites “…U.S. Patent Application No. 18/432,161 filed on February 5, 2024, which is a continuation of…” where it should instead recite “…U.S. Patent Application No. 18/432,161 filed on February 5, 2024, now issued as U.S. Patent No. 12,282,756, which is a continuation of…”
Appropriate correction is required.
The disclosure is objected to because of the following informalities: According to MPEP 608.01(m), the present Office practice is to insist that each claim must be the object of a sentence starting with “I (or we) claim,” “The invention claimed is” (or the equivalent). Thus, the heading simply stating “CLAIMS:” is not sufficient.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, and 6 of U.S. Patent No. 9,235,871; claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, and 5 of U.S. Patent No. 10,101,977; claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 10, 11, and 13 of U.S. Patent No. 10,949,177; claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, and 11 of U.S. Patent No. 11,907,691; and claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,282,756. Although the claim at issue is not identical, they are not patentably distinct from each other because the limitations of the instant claim are essentially covered by the limitations of the patent claims, as shown in the tables below.
19/088,739
Claim 1
9,235,871
Claims 1, 4-6
10,101,977
Claims 1, 4, 5
10,949,177
Claims 1, 6, 10, 11, 13
11,907,691
Claims 1, 3, 4, 11
12,282,756
Claim 1
19/088,739 (Claim 1)
9,235,871 (Claims 1 and 4-6)
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a second set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
A system…to execute a program, the system comprising: a general purpose central processing unit (CPU) device executing commands in a CPU programming language; a graphic processing unit (GPU) device executing commands in a GPU programming language that is distinct from the CPU programming language; (Claim 1)
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
a command processor accessible to the CPU device and the GPU device, the command processor managing jobs from the program…a data compiler…to convert program data for the commands into a first data format readable by the CPU programming language and a second data format readable by the GPU programming language (Claim 1)
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs,
a graphics transfer memory coupled to the CPU device and the GPU device, the graphics transfer memory storing resources for the commands (Claim 4)
the graphics transfer memory includes frame graphics transfer memory (Claim 5)
wherein the stored commands include the first set of one or more commands or the second set of one or more commands,
first sequence of commands…second sequence of commands (Claim 1)
wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and
commands…in a state free command format (Claim 1)
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
wherein the command format maps the commands to a plurality of different hardware platforms (Claim 6)
19/088,739 (Claim 1)
10,101,977 (Claims 1, 4, and 5)
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a second set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
A system…to execute a program, the system comprising: a first processing unit device executing commands in a first programming language; a second processing unit device executing commands in a second programming language that is distinct from the first programming language; (Claim 1)
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
a command processor accessible to the first processing unit device and a second processing unit device, the command processor managing jobs from the program…data compiler…to convert program data for the commands into a first data format…for the first programming language…and a second data format…for the second programming language (Claim 1)
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs,
a transfer memory accessible by the first processing unit device and the second processing unit device, the transfer memory storing resources for the commands (Claim 1)
the transfer memory includes frame graphics transfer memory (Claim 4)
wherein the stored commands include the first set of one or more commands or the second set of one or more commands, wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and
commands from the jobs in a state free command format…a first sequence of commands…a second sequence of commands… in the command format (Claim 1)
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
wherein the command format maps the commands to a plurality of different hardware platforms (Claim 5)
19/088,739 (Claim 1)
10,949,177 (Claims 1, 6, 10, 11, and 13)
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a second set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
A system…to execute a program, the system comprising: a first processing unit device configured to execute commands in a first programming language; a second processing unit device configured to execute commands in a second programming language that is distinct from the first programming language (Claim 1)
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
a command processor configured to generate one or more commands for execute by the first processing unit device or the second processing unit device; a data compiler configured to convert program data for the one or more commands int a first data format usable by the first programming language and a second data format usable by the second programming language; (Claim 1)
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs,
a transfer memory accessible by the first processing unit device and the second processing unit device, the transfer memory being configured to store the program data (Claim 1)
the transfer memory includes (i) frame graphics transfer memory (Claim 10)
wherein the stored commands include the first set of one or more commands or the second set of one or more commands,
wherein the one or more commands…include a first sequence of commands for execution by the first processing unit device and a second sequence of commands for execution by the second processing unit device (Claim 6)
wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and
wherein the commands are in a state-free command format (Claim 11)
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
wherein the command format maps each of the one or more commands to a plurality of different hardware platforms (Claim 13)
19/088,739 (Claim 1)
11,907,691 (Claims 1, 3, 4, and 11)
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a second set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
A system for executing a program, the system comprising: a first processing unit device configured to execute a first sequence of one or more commands in a first programming language; a second processing unit device configured to execute a second sequence of one or more commands in a second programming language that is distinct from the first programming language; (Claim 1)
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
convert the program data into (a) a first data format usable by the first programming language and (b) a second data format usable by the second programming language (Claim 1)
the command process is configured to be accessible by both the first processing unit device and the second processing unit device (Claim 3)
the command processor is configured to manage jobs for the program (Claim 4)
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs, wherein the stored commands include the first set of one or more commands or the second set of one or more commands,
a transfer memory accessible by the first processing unit device and the second processing unit device, the transfer memory being configured to store program data usable by (i) the first processing unit device to execute the first set of one or more commands, (ii) the second processing unit device to execute the second set of one or more commands (Claim 1)
the transfer memory includes (i) frame graphics transfer memory (Claim 11)
wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and
wherein the first sequence of one or more commands, the second sequence of one or more commands, or both, include commands in a state-free command format, and (Claim 1)
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
wherein the state-free command format maps each of the at least some of the commands in the first sequence of one or more commands and the second sequence of one or more commands to a plurality of different hardware platforms. (Claim 1)
19/088,739 (Claim 1)
12,282,756 (Claim 1)
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a send set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
A system for executing a program by a first processing unit device configured to execute a first set of one or more commands in a first programming language and a second processing unit device configured to execute a send set of one or more commands in a second programming language that is distinct from the first programming language, the system comprising:
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit device or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs,
a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit device or the second processing unit device, the transfer memory comprising (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs,
wherein the stored commands include the first set of one or more commands or the second set of one or more commands,
wherein the stored commands include the first set of one or more commands or the second set of one or more commands,
wherein the first set of one or more commands, the second set of one or more commands or both, include commands in a state-free command format, and
wherein the first set of one or more commands, the second set of one or more commands or both, include commands in a state-free command format, and
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luk (US 20100156888A1), Li (US008711159B2), and Bolz (US 20110242118A1).
Luk teaches a system for executing a program by a first processing unit device (CPU) configured to execute a first set of one or more commands in a first programming language and a second processing unit device (GPU) configured to execute a second set of one or more commands in a second programming language that is distinct from the first programming language (features of a current threading API for CPU processors (such as, e.g., Threading Building Blocks (TBB)), features of a current threading API for GPUs (such as, e.g., CUDA API), [0017]), the system comprising: a command processor accessible to the first processing unit device and the second processing unit device and configured to manage one or more jobs from the program and translate commands associated with the one or more jobs into a format associated with the first programming language or the second programming language; and wherein the command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms (compiler 205 generates TBB and CUDA source codes from the application code program(s) 140 on the fly and then uses system compilers (such as, e.g., a CPU C compiler and/a GPU C compiler) to generate the final machine codes, [0030], features of a current threading API for CPU processors (such as, e.g., Threading Building Blocks (TBB)), features of a current threading API for GPUs (such as, e.g., CUDA API), [0017]).
However, Luk does not teach a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit device or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs, wherein the stored commands include the first set of one or more commands or the second set of one or more commands. However, Li teaches a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit device (110) or the second processing unit device (150), the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs, wherein the stored commands include the first set of one or more commands or the second set of one or more commands (when the application 105 executes on the CPU 110, it generates low level graphics commands and transmits them in command buffers 130 to the GPU 150, GPU 150 parses the command buffers, loads the graphics data and then performs the corresponding rendering tasks, col. 2, line 66-col. 3, line 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Luk to include a transfer memory communicatively coupled to the command processor and accessible to either the first processing unit device or the second processing unit device, the transfer memory comprising at least one of (i) a frame graphics transfer memory, (ii) a frame command transfer memory, (iii) an owner graphics transfer memory, and (iv) an owner command memory, the transfer memory being configured to store the commands associated with the one or more jobs, wherein the stored commands include the first set of one or more commands or the second set of one or more commands because Li suggests that this is a conventional CPU-GPU arrangement of a computing device, and thus this arrangement is well-known in the art (col. 2, lines 53-56).
However, Luk and Li do not teach wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to the plurality of different hardware platforms. However, Bolz teaches wherein the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format (stateless graphics refers to a new programming model for the GPU 150, where all graphics workloads to be processed by the GPU 150 are self-contained, i.e., include all the state information that is needed to process the graphics workloads, each draw call could include all the state needed for the draw call, in such a model, the state information needed to process a graphics workload does not need to be tracked by GPU driver 118, [0035]). Since Luk teaches wherein the command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms [0030, 0017], this teaching of the state-free command format from Bolz can be implemented into the device of Luk so that the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to a plurality of different hardware platforms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Luk and Li so that the first set of one or more commands, the second set of one or more commands, or both, include commands in a state-free command format, and wherein the state-free command format maps each of at least some of the commands in the first set of one or more commands and the second set of one or more commands to the plurality of different hardware platforms because Bolz suggests that this allows the generation and execution of the different graphics workloads to be more independently ordered and parallelizable [0035].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONI HSU whose telephone number is (571)272-7785. The examiner can normally be reached M-F 10am-6:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kee Tung can be reached at (571)272-7794. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JH
/JONI HSU/Primary Examiner, Art Unit 2611
Prosecution Insights