Detailed Action
The instant application having Application No. 19/088,805 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 3/24/25. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 3/24/25 are acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Roberts et al. (U.S. Patent Application Publication No. 2021/0271614), herein referred to as Roberts et al.
Referring to claim 16, Roberts et al. disclose a chiplet-based system (see para. 15, where the memory system contains chips), comprising: a first memory; a second memory; (see fig. 2, showing multiple memory devices) a primary chiplet die and a secondary chiplet die (see fig. 1, showing host and memory subsystems and para. 15, where the memory sub-system may include one or more memory devices (chips or integrated circuits)) configured to implement an at least one processor that operates according to an operating system (see para. 53, where the host performs operations to determine output data by executing instructions in a processor, which would need an operating system) and configured to access the first memory and the second memory through a unified memory mapping (see fig. 1 and para. 75, showing memory bus 20 and fig. 2, where the memory system may be coupled to the host by a memory bus), wherein the primary chiplet die includes: an at least one first client implemented by the operating system and configured to access the first memory and the second memory through the unified memory mapping (see para. 53, where the host performs various operations, for example, to determine output data by executing instructions in a processor to perform corresponding data processing operation on input data); a first memory controller (see fig. 1, showing memory controllers 26 and 32); an aggregation entity (see para. 34, where there is a calibration process performed at least in part by a calibration system) configured to aggregate a memory access bandwidth for the at least one first client in the primary chiplet die (see fig. 4, processor core 1, 72P) and a memory access bandwidth for an at least one second client in the secondary chiplet die (see fig. 4, processor core P, 72P) to form an aggregated bandwidth and configured to determine a memory clocking frequency for the first memory and the second memory that satisfies the aggregated bandwidth; and a first transition entity configured to command the first memory controller to transition the first memory to the memory clocking frequency (see fig. 2, para. 36-40, where the calibration process determines the performance mode memory bus bandwidth by summing together the bus bandwidths with each memory type. The calibration process may then determine the bus clock frequency by dividing the target bus bandwidth by the bit width of the bus and the bus cycle duration).
As to claim 17, Roberts et al. also disclose the chiplet-based system of claim 16, wherein the secondary chiplet die includes: a second memory controller; and a second transition entity configured to command the second memory controller to transition the second memory to the memory clocking frequency (see fig. 2, showing memory controller 32 with memory device clocks for memory device 1 18A and memory device M 18M).
As to claim 19, Roberts et al. also disclose the chiplet-based system of claim 16, wherein the aggregation entity and the first transition entity are independent from the operating system (see fig. 1 and 2, where host side memory controller 26 and memory side memory controller 32 are independent of processing circuitry 16 and therefore from the operating system).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7 and 10-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Li et al. (U.S. Patent Application Publication No. 2017/0277460), herein referred to as Li et al.
Referring to claim 1, Roberts et al. disclose as claimed, a chiplet-based system (see para. 15, where the memory system contains chips), comprising: a first memory ;a second memory (see fig. 2, showing multiple memory devices); a primary chiplet die including: an at least one first memory client configured to access the first memory and the second memory through a unified memory map (see fig. 1, showing host and memory subsystems and para. 15, where the memory sub-system may include one or more memory devices (chips or integrated circuits. See para. 53, where the host performs various operations, for example, to determine output data by executing instructions in a processor to perform corresponding data processing operation on input data), (see fig. 4, processor core 1, 72P); a first memory controller (see fig. 1, showing memory controllers 26 and 32); and a first transition entity configured to command the first memory controller to transition the first memory to a memory clocking frequency (see fig. 2, para. 36-40, where the calibration process determines the performance mode memory bus bandwidth by summing together the bus bandwidths with each memory type. The calibration process may then determine the bus clock frequency by dividing the target bus bandwidth by the bit width of the bus and the bus cycle duration); a second memory controller (see fig. 1, showing memory controllers for the host and memory subsystem); and a second transition entity configured to command the second memory controller to transition the second memory to the memory clocking frequency (see fig. 2, para. 36-40, where the calibration process determines the performance mode memory bus bandwidth by summing together the bus bandwidths with each memory type. The calibration process may then determine the bus clock frequency by dividing the target bus bandwidth by the bit width of the bus and the bus cycle duration. The memory bus and clock frequencies of each controller would need to be changed), wherein the primary chiplet die further includes: an aggregation entity (see para. 34, where there is a calibration process performed at least in part by a calibration system) configured to aggregate the bandwidth from each first memory and from each second memory to form an aggregated bandwidth and to determine the memory clocking frequency responsive to the aggregated bandwidth (see fig. 2, para. 36-40, where the calibration process determines the performance mode memory bus bandwidth by summing together the bus bandwidths with each memory type. The calibration process may then determine the bus clock frequency by dividing the target bus bandwidth by the bit width of the bus and the bus cycle duration).
Roberts et al. disclose the claimed invention except for wherein each at least one first memory client is further configured to access the first memory and the second memory according to a bandwidth; a secondary chiplet die including: an at least one second memory client configured to access the first memory and the second memory through the unified memory map, wherein each at least one second memory client is further configured to access the first memory and the second memory according to a bandwidth; aggregating the bandwidth from each of a first memory and second memory client.
However, Li et al. disclose wherein each at least one first memory client is further configured to access the first memory and the second memory according to a bandwidth (see para. 28, where each client may have memory performance and bandwidth requirements. When combined with Roberts, which teaches accessing multiple memories according to total bandwidth, this would allow each client to access multiple memories according to a bandwidth); a secondary chiplet die including: an at least one second memory client configured to access the first memory and the second memory through the unified memory map (see para. 21, where an SoC comprises multiple memory clients on chiplet dies which would access memories through a unified memory map), wherein each at least one second memory client is further configured to access the first memory and the second memory according to a bandwidth (see para. 28, where each client may have memory performance and bandwidth requirements. When combined with Roberts, which teaches accessing multiple memories according to total bandwidth, this would allow each client to access multiple memories according to a bandwidth); aggregating the bandwidth from each of a first memory and second memory client (see para. 28, where the bandwidth requirement for each client is summed to find the total cache bandwidth requirement, and then used to find the cache frequency).
Roberts et al. and Li et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Li et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise each at least one first memory client is further configured to access the first memory and the second memory according to a bandwidth; a secondary chiplet die including: an at least one second memory client configured to access the first memory and the second memory through the unified memory map, wherein each at least one second memory client is further configured to access the first memory and the second memory according to a bandwidth; aggregating the bandwidth from each of a first memory and second memory client, as taught by Li et al., in order to allow for multiple clients to aggregate bandwidth and determine memory bandwidth depending on clients to better serve and be responsive to their demands.
As to claim 2, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 1, wherein the first memory comprises a first double data rate (DDR) memory and wherein the second memory comprises a second DDR memory (see Li et al., para. 4, where the memory system may be a DDR memory system).
As to claim 3, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 2, wherein the first DDR memory and the second DDR memory each comprises a DDR dynamic random-access memory (see Li et al., para. 4, where the memory system may be a DDR memory system, which is a type of DRAM system).
As to claim 4, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 1, wherein the first transition entity is further configured to coordinate with the second transition entity so that the first memory and the second memory both transition to the memory clocking frequency in parallel (see Roberts et al., para. 37, where the calibration process determines a performance mode memory bus clock frequency and communication cycle to be used with each of the multiple different memory types in the memory system. The target memory frequency for multiple memories is set at the same time).
As to claim 5, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 1, wherein the first transition entity, the second transition entity, and the aggregation entity are independent from an operating system for the chiplet-based system (see Roberts et al., fig. 1 and 2, where host side memory controller 26 and memory side memory controller 32 are independent of processing circuitry 16 and therefore from the operating system).
As to claim 7, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 1, wherein the aggregation entity, the first transition entity, and the second transition entity each comprises a hardware sequencer (see Roberts et al., para. 15, where the memory system may include chips or integrated circuits, which would be hardware. Also see Li et al., para. 52-53, where the memory device may be implemented with hardware or software).
As to claim 10, Roberts et al. and Li et al. also disclose the chiplet-based system of claim 1, further comprising: an at least one bus coupled between the primary chiplet die and the secondary chiplet die (see Roberts et al. fig. 1 and 2, showing a memory bus that couples the memory devices to the host and memory bus interface as well as to each other).
Referring to claim 11, Roberts et al. disclose as claimed, a method of operation for a chiplet-based system (see para. 15, where the memory system contains chips), comprising: accessing a first memory and a second memory through a unified memory mapping for an at least one first client in a primary chiplet die and for an at least one second client in a secondary chiplet die (see fig. 1, showing host and memory subsystems and para. 15, where the memory sub-system may include one or more memory devices (chips or integrated circuits. See para. 53, where the host performs various operations, for example, to determine output data by executing instructions in a processor to perform corresponding data processing operation on input data), (see fig. 4, processor core 1, 72P), determining a memory clocking frequency that satisfies the aggregated bandwidth; and transitioning the first memory and the second memory to both operate according to the memory clocking frequency (see fig. 2, para. 36-40, where the calibration process determines the performance mode memory bus bandwidth by summing together the bus bandwidths with each memory type. The calibration process may then determine the bus clock frequency by dividing the target bus bandwidth by the bit width of the bus and the bus cycle duration).
Roberts et al. disclose the claimed invention except for wherein each at least one first client and each at least one second client accesses the first memory and the second memory according to a corresponding bandwidth; aggregating the corresponding bandwidth from each at least one first client and from each at least one second client to form an aggregated bandwidth
However, Li et al. disclose wherein each at least one first client and each at least one second client accesses the first memory and the second memory according to a corresponding bandwidth (see para. 28, where each client may have memory performance and bandwidth requirements. When combined with Roberts, which teaches accessing multiple memories according to total bandwidth, this would allow each client to access multiple memories according to a bandwidth); aggregating the corresponding bandwidth from each at least one first client and from each at least one second client to form an aggregated bandwidth (see para. 28, where the bandwidth requirement for each client is summed to find the total cache bandwidth requirement, and then used to find the cache frequency).
Roberts et al. and Li et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Li et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise wherein each at least one first client and each at least one second client accesses the first memory and the second memory according to a corresponding bandwidth; aggregating the corresponding bandwidth from each at least one first client and from each at least one second client to form an aggregated bandwidth, as taught by Li et al., in order to allow for multiple clients to aggregate bandwidth and determine memory bandwidth depending on clients to better serve and be responsive to their demands.
As to claim 12, Roberts et al. and Li et al. also disclose the method of claim 11, further comprising: implementing the at least one first client using instructions for an operating system for the chiplet-based system, wherein aggregating the corresponding bandwidth, determining the memory clocking frequency, and transitioning the first memory and the second memory are independent from the operating system (see Roberts et al., fig. 1 and 2, where host side memory controller 26 and memory side memory controller 32 are independent of processing circuitry 16 and therefore from the operating system).
As to claim 13, Roberts et al. and Li et al. also disclose the method of claim 11, wherein the transitioning of the first memory to operate according to the memory clocking frequency occurs in parallel with the transitioning of the second memory to operate according to the memory clocking frequency (see Roberts et al., para. 37, where the calibration process determines a performance mode memory bus clock frequency and communication cycle to be used with each of the multiple different memory types in the memory system. The target memory frequency for multiple memories is set at the same time).
As to claim 14, Roberts et al. and Li et al. also disclose the method of claim 11, wherein the transitioning of the first memory comprises transitioning a first double data rate dynamic random-access memory to operate according to the memory clocking frequency, and wherein the transitioning of the second memory comprises transitioning a second double data rate dynamic random- access memory to operate according to the memory clocking frequency (see Roberts et al., para. 37, where a performance mode memory bus clock frequency is set which may apply to both a first and second memory).
As to claim 15, Roberts et al. and Li et al. also disclose the method of claim 11, wherein the aggregating of the corresponding bandwidth from each at least one first client and from each at least one second client comprises summing the corresponding bandwidth from each at least one first client and from each at least one second client (see Li et al., where total bandwidth may be determined by a sum of all of the client’s bandwidth requirements. Also see Roberts et al., where para. 37, where total bandwidth is determined by summing).
As to claim 18, Roberts et al. disclose the claimed invention except for the chiplet-based system of claim 16, wherein the first memory and the second memory each comprises a DDR DRAM.
However, Li et al. disclose wherein the first memory and the second memory each comprises a DDR DRAM (see para. 1-2, where DDR DRAM may be used).
Roberts et al. and Li et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Li et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise , wherein the first memory and the second memory each comprises a DDR DRAM, as taught by Li et al., in order to allow for increased data rate and better performance. Using DDR DRAM is well known in the art and would be obvious to implement with Roberts et al.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Li et al. and in view of Athreya et al. (U.S. Patent No. 11,769,557), herein referred to as Athreya et al.
As to claim 8, Roberts et al. and Li et al. disclose the claimed invention except for the chiplet-based system of claim 1, wherein the aggregation entity, the first transition entity, and the second transition entity each comprises a state machine.
However, Athreya et al. disclose wherein the aggregation entity, the first transition entity, and the second transition entity each comprises a state machine (see col. 5, lines 8-25, where the controller may be implemented with software, firmware or hardware, including state machines or an embedded controller. When applied to Roberts et al. and Li et al., this would allow for their logic to also be implemented in a state machine or embedded controller among many choices).
Roberts et al. and Athreya et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Athreya et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise wherein the aggregation entity, the first transition entity, and the second transition entity each comprises a state machine, as taught by Athreya et al., in order to allow for clear rules and easier debugging for logic. Using state machines is well known in the art and would be an obvious way to implement the logic in Roberts et al.
As to claim 9, Roberts et al. and Li et al. disclose the claimed invention except for the chiplet-based system of claim 1, wherein the aggregation entity, the first transition entity, and the second transition entity each comprises an embedded micro- controller.
However, Athreya et al. disclose wherein the aggregation entity, the first transition entity, and the second transition entity each comprises an embedded micro- controller (see col. 5, lines 8-25, where the controller may be implemented with software, firmware or hardware, including state machines or an embedded controller. When applied to Roberts et al. and Li et al., this would allow for their logic to also be implemented in a state machine or embedded controller among many choices).
Roberts et al. and Athreya et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Athreya et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise wherein the aggregation entity, the first transition entity, and the second transition entity each comprises an embedded micro- controller, as taught by Athreya et al., in order to allow a compact size and low power consumption. Using embedded micro controllers is well known in the art and would be an obvious way to implement the logic in Roberts et al.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Li et al. and in view of Kawakami (U.S. Patent Application Publication No. 2015/0106635), herein referred to as Kawakami.
As to claim 6, Roberts et al. and Li et al. disclose the claimed invention except for the chiplet-based system of claim 5, wherein the aggregation entity is further configured to inform the operating system that a transition by the first memory and by the second memory to the memory clocking frequency is completed.
However, Kawakami disclose wherein the aggregation entity is further configured to inform the operating system that a transition by the first memory and by the second memory to the memory clocking frequency is completed (see para. 149, where after a change in clock frequency completes, a signal is output that confirms that the clock frequency has changed and is output throughout the circuit. When combined with Roberts and Li, this would enable the aggregation entity to inform the OS that a transition of the memory clock frequency has completed).
Roberts et al. and Athreya et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and Athreya et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise wherein the aggregation entity is further configured to inform the operating system that a transition by the first memory and by the second memory to the memory clocking frequency is completed, as taught by Kawakami, in order to let the other system components and OS know to coordinate data transmission more efficiently.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Li et al. and in view of You (U.S. Patent Application Publication No. 2021/0357155), herein referred to as You.
As to claim 20, Roberts et al. and Li et al. disclose the claimed invention except for the chiplet-based system of claim 16, wherein the first memory and the second memory are fully interleaved.
However, You discloses wherein the first memory and the second memory are fully interleaved (see para. 72, where memories are fully interleaved).
Roberts et al. and You et al. are analogous art because they are from the same field of endeavor of memory systems (see Roberts et al., abstract and You et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Roberts et al. to comprise wherein the first memory and the second memory are fully interleaved, as taught by You, in order to maximize performance (see You, para. 72).
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are the subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
