DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 33 is/are allowed.
Claim(s) 8, 11-16, 24 and 27-32 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim interpretation under 35 U.S.C. 112(f) of claims 17-32 may be withdrawn by amending the claim to recite sufficient structure or material, such as a hardware module or circuits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 24 recites the limitation "the means for updating the transaction entry" in line 1. There is insufficient antecedent basis for this limitation in the claim. Amending the dependency of the claim to claim depend from claim 23 would overcome the rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 10, 17-20, 22, 23 and 26 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Moyer (US 2018/0018264).
Regarding claim(s) 1 and 17, Moyer teaches:
A method for cache miss monitoring and fulfillment, comprising: receiving, from a processing unit, a cache access request; determining, based on a cache failing to fulfill the cache access request, that a cache miss has occurred; [0011] While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, a cache controller issues a memory access request for the data to a higher level of the memory hierarchy.
populating a request buffer based on the cache miss and the cache access request; [0022] The cache controller 120 also stores in as a pending miss buffer 130 a cache entry (CE) tag 165 including the data index and location information concerning the cache entry that has been assigned to the cache line that is being fetched. For example, in some embodiments, the cache controller 120 stores in the pending miss buffer 130 a cache entry tag 165 including the data index and the cache way that has been assigned in cache memory 140 to the cache line that is being fetched.
populating a transaction buffer with a transaction entry for the request buffer based on the cache miss and the cache access request; [0022] While the requested cache line is in the process of being retrieved (fetched) from main memory 150 by the processor core 110, the cache controller 120 assigns a cache entry to the cache line that is being fetched. In some embodiments, the cache controller 120 assigns the cache entry corresponding to the cache set and way in which the cache line will be stored once it has been retrieved from main memory 150.
determining by the request buffer, that information requested in the cache access request should be retrieved from main memory; [0021] If the requested cache line is not found in the cache memory 140, the cache controller 120 provides the memory access request 102 to the main memory 150.
determining, by the transaction buffer if information was not retrieved, that the cache access request satisfies criteria for creating a cache miss tag; creating the cache miss tag based on the cache access request; and storing the cache miss tag in a portion of the cache. [0012] also stores at the cache entry an indicator that a memory access request for the data is pending at the main memory. In some embodiments, the indicator is a miss tag including the main memory address of the data being fetched as well as status information indicating that the data is the subject of a pending memory access request. [0022] The cache controller 120 stores at the cache entry a miss tag 147 including the main memory address of the cache line that is being fetched, and a status bit indicating that the cache line is the subject of a pending cache miss.
Regarding claim(s) 2 and 18, Moyer teaches:
further comprising: accessing, by the request buffer, a main memory for information requested in the cache access request; and updating the transaction buffer based on whether the request buffer accessed the information. [0025] When the main memory 150 retrieves the cache line at the main memory address targeted by the request and provides the cache line to cache memory 140, the cache controller 120 compares the data index of the cache line against the cache entry tags 165 stored in the pending miss buffer 130. The cache controller matches the data index of the cache line to the stored cache entry tag, and reads from the cache entry tag 165 the cache entry in the cache memory 140 that has been assigned to store the cache line. The cache controller 120 stores the cache line at the previously assigned set and way of the cache entry and updates the status bit to a valid state, indicating that the cache line is present in the cache memory 140.
Regarding claim(s) 3 and 19, Moyer teaches:
further comprising updating the cache with the information when the request buffer successfully accessed the information. [0025] When the main memory 150 retrieves the cache line at the main memory address targeted by the request and provides the cache line to cache memory 140, the cache controller 120 compares the data index of the cache line against the cache entry tags 165 stored in the pending miss buffer 130. The cache controller matches the data index of the cache line to the stored cache entry tag, and reads from the cache entry tag 165 the cache entry in the cache memory 140 that has been assigned to store the cache line. The cache controller 120 stores the cache line at the previously assigned set and way of the cache entry and updates the status bit to a valid state, indicating that the cache line is present in the cache memory 140.
Regarding claim(s) 4 and 20, Moyer teaches:
further comprising modifying the transaction entry to refer to the cache miss tag. [0012] also stores at the cache entry an indicator that a memory access request for the data is pending at the main memory. In some embodiments, the indicator is a miss tag including the main memory address of the data being fetched as well as status information indicating that the data is the subject of a pending memory access request.
Regarding claim(s) 6 and 22, Moyer teaches:
further comprising: accessing the main memory for information requested in the cache access request based on the cache miss tag; and updating the cache with the information when the information is successfully accessed. [0025] When the main memory 150 retrieves the cache line at the main memory address targeted by the request and provides the cache line to cache memory 140, the cache controller 120 compares the data index of the cache line against the cache entry tags 165 stored in the pending miss buffer 130. The cache controller matches the data index of the cache line to the stored cache entry tag, and reads from the cache entry tag 165 the cache entry in the cache memory 140 that has been assigned to store the cache line. The cache controller 120 stores the cache line at the previously assigned set and way of the cache entry and updates the status bit to a valid state, indicating that the cache line is present in the cache memory 140.
Regarding claim(s) 7 and 23, Moyer teaches:
further comprising updating the transaction entry based on the cache being updated. [0025] When the main memory 150 retrieves the cache line at the main memory address targeted by the request and provides the cache line to cache memory 140, the cache controller 120 compares the data index of the cache line against the cache entry tags 165 stored in the pending miss buffer 130. The cache controller matches the data index of the cache line to the stored cache entry tag, and reads from the cache entry tag 165 the cache entry in the cache memory 140 that has been assigned to store the cache line. The cache controller 120 stores the cache line at the previously assigned set and way of the cache entry and updates the status bit to a valid state, indicating that the cache line is present in the cache memory 140.
Regarding claim(s) 10 and 26, Moyer teaches:
wherein the transaction entry comprises a location of the cache access request within the request buffer. [0022] The cache controller 120 also stores in as a pending miss buffer 130 a cache entry (CE) tag 165 including the data index and location information concerning the cache entry that has been assigned to the cache line that is being fetched. For example, in some embodiments, the cache controller 120 stores in the pending miss buffer 130 a cache entry tag 165 including the data index and the cache way that has been assigned in cache memory 140 to the cache line that is being fetched.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 9, 21 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moyer (US 2018/0018264) in view of Punniyamurthy (US 2023/0169015).
Regarding claim(s) 5 and 21, Moyer does not explicitly teach, but Punniyamurthy teaches:
further comprising: deleting or invalidating the transaction entry; and populating a new transaction entry in the transaction buffer referring to the cache miss tag. [0023] When the cache controller adds new data to an already full cache, the cache controller selects a victim line to remove from the cache according to a replacement policy, which is a set of rules for identifying the least valuable data to keep in the cache (e.g., data that is least likely to be accessed again in the near future).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to combine the cache memory system/method of Moyer with the cache/buffer entry eviction system/method of Punniyamurthy. The rationale for doing so would have been that the technique of deleting and replacing a cache/buffer entry on based eviction policies would provide a reliable, well-known means to operate cache/system that increases memory access performance with a reasonable expectation of success.
Regarding claim(s) 9 and 25, Moyer does not explicitly teach, but Punniyamurthy teaches:
further comprising evicting a cache entry based on an eviction criteria, wherein the eviction criteria comprises one of a predicted time until overwriting of an entry in the request buffer, a sequence of the cache access request within a plurality of cache access requests of the request buffer, a notification, or a time since the entry in the request buffer was created. [0023] When the cache controller adds new data to an already full cache, the cache controller selects a victim line to remove from the cache according to a replacement policy, which is a set of rules for identifying the least valuable data to keep in the cache (e.g., data that is least likely to be accessed again in the near future).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Patel (US 5353426): discloses cache miss buffer system that stores cache miss information.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133
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