Prosecution Insights
Last updated: October 04, 2026
Application No. 19/089,043

METHOD FOR MANUFACTURING WIRING SUBSTRATE

Final Rejection §103§112
Filed
Mar 25, 2025
Priority
Mar 26, 2024 — JP 2024-050011
Examiner
WIECZOREK, MICHAEL P
Art Unit
1712
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Ibiden Co., Ltd.
OA Round
2 (Final)
55%
Grant Probability
Moderate
3-4
OA Rounds
1y 8m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
497 granted / 900 resolved
-9.8% vs TC avg
Strong +17% interview lift
Without
With
+16.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
39 currently pending
Career history
939
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
51.3%
+11.3% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
31.0%
-9.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 900 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims By amendment filed August 07, 2026, claims 1, 6, 12 and 17 have been amended. Claims 1 through 20 are currently pending. Response to Arguments Applicant's arguments filed August 07, 2026, have been considered but they are not fully persuasive. Applicant’s arguments with respect to the rejection(s) of claim(s) under 103 have been fully considered and are persuasive as none of the references teach that the resist layer was exposed to direct imaging exposure without the use of a photomask. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the previously cited prior art and new prior art necessitated by the amendments to the claims. As will be discussed further within this Office Action, Saitou (U.S. Patent # 5,162,240) teaches a method for manufacturing a multilayer wiring substrate wherein a resist layer used in forming conductive/metal patterns was formed by direct imaging exposure in which a photomask was not used by irradiating the resist with an electron beam to form a negative type resist pattern. Furthermore, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant’s arguments against the 112(b) rejection of the claims are not persuasive because it is not clear how the new limitation “in a range” overcomes the rejections. The amendments to claims 1, 6, 12 and 17 have not overcome the 112(b) rejections. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 is indefinite because the claim requires that the plurality of wirings have a minimum width of 2 micron or less and it is not clear what the minimum width for the wirings have to be since the minimum value for this variable is a range. For the purposes of this examination this limitation will be taken to require that the minimum width for each wiring is 2 microns. Claim 1 is indefinite because the claim requires that the plurality of wirings have a minimum inter-wiring distance of 2 micron or less and it is not clear what the minimum distance has to be between each wiring since the minimum value for this variable is a range. For the purposes of this examination this limitation will be taken to require that the minimum inter-wiring distance between each wiring is 2 microns. Claim 6 is indefinite because the limitation of the claim contradicts specification of the present invention as originally filed. Claim 6 requires that the surface of the build-up part facing the glass substrate has a flatness of ±2.5 microns or less. This contradicts the specification of the present application as originally filed which discloses that the first surface of the first support substrate comprising the glass substrate has a flatness of ±2.5 microns or less (Page 14 Lines 12-24 of the specification of the present application as originally filed). For the purposes of this examination this limitation will be taken to require that the surface which the build-up part was formed has a flatness of ±2.5 microns or less. Claim 12 is indefinite because the limitation of the claim contradicts specification of the present invention as originally filed. Claim 12 requires that the surface of the build-up part facing the glass substrate has a flatness of ±2.5 microns or less. This contradicts the specification of the present application as originally filed which discloses that the first surface of the first support substrate comprising the glass substrate has a flatness of ±2.5 microns or less (Page 14 Lines 12-24 of the specification of the present application as originally filed). For the purposes of this examination this limitation will be taken to require that the surface which the build-up part was formed has a flatness of ±2.5 microns or less. Claim 17 is indefinite because the limitation of the claim contradicts specification of the present invention as originally filed. Claim 17 requires that the surface of the build-up part facing the glass substrate has a flatness of ±2.5 microns or less. This contradicts the specification of the present application as originally filed which discloses that the first surface of the first support substrate comprising the glass substrate has a flatness of ±2.5 microns or less (Page 14 Lines 12-24 of the specification of the present application as originally filed). For the purposes of this examination this limitation will be taken to require that the surface which the build-up part was formed has a flatness of ±2.5 microns or less. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 3, 6, 7, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Toba et al (U.S. Patent Publication No. 2023/0209725) in view of Furusawa et al (U.S. Patent Publication No. 2016/0113110) and Saitou et al (U.S. Patent # 5,162,240). In the case of claim 1, Toba teaches a method for manufacturing a wiring substrate in the form of a wiring structure (Abstract). The method of Toba comprised preparing/providing an insulating substrate 11 comprising glass by covering the glass substrate 11 with a conductive layer 12 (Page 2 Paragraph 0032). Toba teaches that the glass substrate/base material was panel shaped with a rectangular main surface/product area (Page 2 Paragraph 0033). Toba further teaches an embodiment wherein the base material had a surface area of 200 mm by 200 mm (Page 10 Paragraph 0150), which was within the required range of each side being in the range of 80 to 240 mm. Toba further teaches having formed a build-up part comprising alternating three or more conductor layer and three or more insulating layers in the form of a multilayer wiring part 7 comprised of a plurality of insulating layers 21, 22 and 23 and conductor layers comprising wirings 5 and 5a (Page 2 Paragraph 0027 and Page 12 Paragraph 0174 and Figure 1-3 and 7). Toba further teaches that the wirings had a width in the range of 1 to 5 microns and a spacing of 10 microns or less (Page 1 Paragraph 0005, Page 4 Paragraph 0059 and Page 9 Paragraph 0132), which overlapped with the required ranges. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). See section 2144.05.I of the MPEP. Toba further teaches that the plurality of wirings were formed using a resist layer 4 having a resist pattern (Page 3 Paragraph 0043) and that forming the resist layer 4 comprised exposing the layer by direct imaging exposure using a photo tool (Page 4 Paragraph 0057). Toba does not teach that the build-up part/multilayer wiring part was formed in such a way that the different in thermal expansion coefficient between the glass substrate and the insulating layers was 13 ppm/℃ or less. Furusawa teaches a wiring substrate in the form of a printed wiring board comprising a substrate and a build-up layer comprising a plurality of conductor layer and insulating layers wherein the difference between the thermal expansion coefficient of the substrate and the insulating layers was 15 ppm/℃ or less in order to suppress warpage then the wiring board was subjected to thermal stress (Page 4 Paragraph 0061). Based on the teachings of Furusawa, at the time the present invention was effectively filed it would have been obvious to one of ordinary skill in the art to have formed the wiring substrate of Toba to have a difference in thermal expansion coefficient between the glass substrate and the insulating layers to be 15 ppm/℃ or less in order to suppress warpage of the wiring substrate during thermal stress. Furthermore, the range of 15 ppm/℃ or less overlapped with the claimed range of 13 ppm/℃ or less and as was discussed previously overlapping ranges are prima facie obvious. Though Toba teaches having formed a resist layer which was exposed to direct imaging Toba does not teach that the direct imaging was conducted without a photomask. However, Toba does teach resist pattern was a negative type and was formed by any method used in the art (Page 4 Paragraph 0057). Saitou teaches a method for forming a multilayer wiring substrate (Abstract and Column 1 Lines 9-15) wherein conductive layers in the form of metal films were formed using a patterned resist layer wherein the resist was a negative type resist resin exposed to direct imaging without the use of a photomask by exposing the resist to an electron beam followed by development of the resist (Column 7 Line 56 through Column 8 Line 26). Based on the teachings of Saitou, at the time the present invention was effectively filed it would have been obvious to one of ordinary skill in the art to have performed direct imaging exposure of the resist layer of Toba in view of Furusawa without the use of a photomask by using an electron beam because this was a known process in the art for patterning a negative type resist layer. As for claim 3, Toba teaches that the glass substrate 1 had a thickness of 0.2 to 2.00 mm (Page 2 Paragraph 0033), which overlapped with the claimed range of 0.7 mm or more and as was discussed previously overlapping ranges are prima facie obvious. As for claims 6 and 17, Toba teaches that the surface the resin layer 21 on which the build-up part was formed had a roughness/flatness of 70 nm or less (Page 3 Paragraph 0047). As for claims 7 and 18, Toba teaches that the wiring 5 had a depth/thickness of 1 to 10 microns and a width of 1 to 10 microns (Page 4 Paragraph 0059) meaning that the wirings had an aspect ratio ranging from 0.1 to 10, which overlapped with the claimed range of 2.0 to 4.0. As was discussed previously overlapping ranges are prima facie evidence. Claims 2, 4, 9, 10, 12, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Toba et al in view of Furusawa et al and Saitou et al as applied to claim 1 above, and further in view of Sugihara (U.S. Patent # 6,492,599). The teachings of Toba in view of Furusawa and Saitou as they apply to claim 1 have been discussed previously and are incorporated herein. In the case claims 2 and 4, as was discussed previously, Toba taught that the substrate was a glass substrate. However, Toba does not teach that the glass substrate had a thermal expansion coefficient of 8 ppm/℃ or more or was comprised of borosilicate glass. Sugihara teaches a multilayer wiring board comprising a glass insulating board/substrate on which was formed a build-up part comprising a plurality of wiring layers and insulating layers (Abstract). Sugihara teaches that the glass substrate had a thermal expansion coefficient of 10 ppm/℃ or less and comprised borosilicate because it comprised silica and boron oxide (Column 11 Line 42 through Column 12 Line 19). Based on the teachings of Sugihara, at the time the present invention was effectively filed it would have been obvious to one of ordinary skill in the art to have used as the glass substrate of Toba in view of Furusawa and Saitou a borosilicate glass substrate having a thermal expansion coefficient of 10 ppm/℃ or less because this was a known glass substrate in the art for forming a multilayer wiring substrate. Furthermore, the thermal expansion coefficient range of 10 ppm/℃ or less overlapped with the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). See section 2144.05.I of the MPEP. As for claims 9, 10, 12 and 13, they are rejected for the same reasons discussed previously in the rejections of claims 3, 4, 6 and 7, respectively. As for claim 15, it is rejected for the same reasons discussed previously in the rejection of claim 4. Claims 5, 8, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Toba et al in view of Furusawa et al and Saitou et al as applied to claims 1 and 3 above, and further in view of Shimizu et al (U.S. Patent # 11,430,725). The teachings of Toba in view of Furusawa and Saitou as they apply to claims 1 and 3 have been discussed previously and are incorporated herein. In the case of claims 5 and 16, Toba does not teach that each insulating layer had a thermal expansion coefficient of 25 ppm/℃ or less. Shimizu, teaches a method for forming a wiring board comprising a plurality of insulating layers (Abstract and Column 1 Lines 19-20) wherein the insulating layer had a thermal expansion coefficient of 10 to 40 ppm/℃ (Column 9 Lines 13-20). Based on the teachings of Shimizu, at the time the present invention was effectively filed it would have been obvious to one of ordinary skill in the art to have formed the insulating layer of Toba in view of Furusawa and Saitou to have a thermal expansion coefficient of 10 to 40 ppm/℃ because this was a known thermal expansion coefficient range in the art for insulating layer used in wiring boards. Furthermore, the taught range of 10 to 40 ppm/℃ overlapped with the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). See section 2144.05.I of the MPEP. As for claims 8 and 19, Toba does not teach having formed a second build-up part on an opposite side of the glass substrate such that the second build-up part comprised an insulating layer having a thickness that was different from each of the thicknesses of the insulating layers in the build-up part. Shimizu teaches having formed a build-up part in the form of a second wiring member 30 on a surface of the substrate 11 of the wiring board wherein the second wiring member comprised insulating layers 32 and 34 (Column 2 Line 64 through Column 3 Line 6, Column 6 Lines 38-49 and Figure 1A). Shimizu further teaches that on an opposite side of the substrate 11 a second build-up part was formed in the form of a solder resist layer 40 which had a thickness different from insulating layers 32 and 34 and acted as an outermost insulating layer (Column 8 Line 44 through Column 9 Line 13 and Figure 1A). Based on the teachings of Shimizu, at the time the present invention was effectively filed it would have been obvious to one of ordinary skill in the art to have formed a second build-up part on the glass substrate of Toba in view of Furusawa and Saitou comprising an insulating layer having a thickness different from the insulating layers of the build-up part on the opposite side of the glass substrate from the build-up part in order to act as an outermost insulating layer. Claims 11, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Toba et al in view of Furusawa et al and Saitou et al and Sugihara as applied to claims 2 and 4 above, and further in view of Shimizu et al. The teachings of Toba in view of Furusawa and Saitou and Sugihara as they apply to claims 2 and 4 have been discussed previously and are incorporated herein. In the case of claims 11 and 20, they are rejected for the same reasons discussed previously in the rejection of claim 5. As for claim 14, it is rejected for the same reasons discussed previously in the rejection of claim 8. Conclusion Claims 1 through 20 have been rejected. No claims were allowed. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P WIECZOREK whose telephone number is (571)270-5341. The examiner can normally be reached Monday - Friday, 6:00 AM - 3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at (571)272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P WIECZOREK/Primary Examiner, Art Unit 1712
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Prosecution Timeline

Mar 25, 2025
Application Filed
May 13, 2026
Non-Final Rejection mailed — §103, §112
Aug 07, 2026
Response Filed
Sep 23, 2026
Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
55%
Grant Probability
72%
With Interview (+16.8%)
3y 2m (~1y 8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 900 resolved cases by this examiner. Grant probability derived from career allowance rate.

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