DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed July 21, 2026 has been entered. Claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre- AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 4, 12, 13, and 15 recite the term "ulayer." "Ulayer" is not a word and it is not clear whether this is a typographical error or applicant is acting as his or her own lexicographer. If applicant is acting as his or her own lexicographer the term must be specifically defined. The term is indefinite because the specification does not clearly define the term. Claims 1, 3, 5, 11, 12, 14, 15, and 20 recite the term "msets." "Msets" is not a word and it is not clear whether this is a typographical error or applicant is acting as his or her own lexicographer. If applicant is acting as his or her own lexicographer the term must be specifically defined. The term is indefinite because the specification does not clearly define the term. If applicant intends to recite the terms "ulayer" and "msets" as abbreviations, then the first occurrence of the abbreviation should accompany the non-abbreviated term.
Claim 1 recites "a controller to disable interaction with the cache address table while
the storage device is in the first state." Claim 3 recites "wherein the controller flushes msets in
the cache address table to the persistent memory and invalidates mset mappings in the cache
address table when the storage device enters the first state." Claim 4 recites "the controller uses
slots in the cache address table for consolidation of the ulayer while the storage device is in the
first state." Claim 5 recites "wherein the controller flushes msets in the cache address table to the
persistent memory and invalidates mset mappings in the cache address table while the storage
device is in the first state." Claim 11 recites "wherein the controller flushes contents in the cache
address table to the persistent memory and invalidates msets mappings in the cache address table
when the storage device enters the first state to maintain a chronology of L2P updates." The
limitations of claims 3-5 and 11 require controller interaction with the cache address table. Therefore, it is not clear whether controller's interaction with the cache address table is disabled or not. Claim 13 recites "a controller to execute the method comprising: disabling interaction with a cache address table while the storage device is in the first state." Therefore, claims 14, 15, and 20 are rejected for at least the same reasons. For examination, the interaction between the controller and the cache address table will not be considered disabled in order to apply art to claims 3-5, 11, 14, 15, and 20.
The term "long-range" in the phrase "long-range random write workload" of claims 2 and
19 is a relative term which renders the claim indefinite. The term "long-range" is not defined by
the claim, the specification does not provide a standard for ascertaining the requisite degree, and
one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The originally filed specification does not provide a definition of long-range and one of ordinary
skill in the art would be unable to determine the degree to which a random write workload is considered long-range. Claim 10 recites the term "long-range" in the phrase "long-range random read workload" and is rejected for at least the same reasons. Claims 7 and 16 recite the term "non-long-range" in the phrase "non-long-range random write workload" and are rejected for at least the same reasons.
Claims 2-11 and 14-20 are further rejected based on their dependency from rejected base claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6-7, 9-10, 12-13, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al. (US 2021/0096984).
Regarding claim 1, Luo et al. disclose:
A storage device (FIG. 1 Memory Device 110) to improve random write processing and performance on the storage device (Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device), the storage device comprises:
a persistent memory to store a logical-to-physical (L2P) table that includes a mapping of logical block addresses in a host command to physical addresses on the persistent memory (FIG. 1 L2P table 161 stored in 3D NAND; [0025] a memory array 120 including, for example, one or more individual memory die (e.g., a stack of three-dimensional (3D) NAND die)… one or more memory die of the memory array 120 can include a first complete L2P table 161 for mapping logical block addresses (LBAs) of the host with physical addresses (PAs) of the flash memory. In certain examples, the table can store the physical address and can be indexed by the logical block address to conserve storage space);
a volatile memory ([0014] Translation tables are generally loaded into an internal memory of the controller…internal memory (e.g., in random access memory (RAM)) including a cache address table to store msets in the L2P table (FIG. 1 Table Cache 130; [0033] the memory controller 115 can include a table cache 130 for storing a portion of the FTL table 161 stored on the die of the memory array) and a ulayer to store updates to msets in the L2P table (FIG. 1 Random Cache 131; [0033] the memory controller 115 can include a random cache 131…the random cache can store mapping information of write requests that have a relatively small amount of non-sequential write data); and
a controller (FIG. 1 Memory Controller 115) to receive a command (FIG. 2 step 203 Receive memory access request from host), track a set of incoming host commands to determine a host workload (FIG. 2 step 205 Read or write request?), trigger a first state on the storage device based on a first host workload (FIG. 2 step 211Write data to memory array), and disable interaction with the cache address table ([0033] the random cache eliminates the need to replace the FTL table cache with mapping information associated with each LBA of each non-sequential write operation) and update the ulayer with mapping information in the host command while the storage device is in the first state (FIG. 2 step 213 Cache LBA and PA in random cache).
Regarding claim 2, Luo et al. further disclose:
The storage device of claim 1, wherein the host workload is a long-range random write workload ([0044] high-speed writes of relatively small amounts of random write; [0016] limit or buffer updating the L2P table cache for a fair portion of random write operations; [0033] For many random write requests, accessing the FTL table 161 for each request can significantly contribute to lowering the memory device performance).
Regarding claim 4, Luo et al. further disclose:
The storage device of claim 1, wherein the controller uses slots in the cache address table (FIG. 1 Table Cache 130) for consolidation of the ulayer (FIG. 1 Random Cache 131) while the storage device is in the first state (FIG. 3 step 327 Update PA in table cache).
Regarding claim 6, Luo et al. further disclose:
The storage device of claim 1, wherein the controller tracks the set of incoming host commands on one of a continuous basis and a periodic basis (FIG. 2 step 205 Read or write request?).
Regarding claim 7, Luo et al. further disclose:
The storage device of claim 1, wherein the controller tracks the set of incoming host commands to determine that the host workload is a non-long-range random write workload and the controller switches to a second state ([0038] when the amount of write data associated with the write access command is larger than a predetermined threshold, the mapping information associated with the write access request and subsequent programming operation can be processed and saved in the table cache or the complete L2P table of the memory array according to conventional methods. As such, the memory controller may compare the amount of write data with the predetermined threshold and cache the LBA and PA in the random cache, at 213, when the amount of write data is less than the predetermined threshold).
Regarding claim 9, Luo et al. further disclose:
The storage device of claim 1, wherein the controller triggers a second state based on the host workload and enables updates to the cache address table ([0038] when the amount of write data associated with the write access command is larger than a predetermined threshold, the mapping information associated with the write access request and subsequent programming operation can be processed and saved in the table cache or the complete L2P table of the memory array according to conventional methods. As such, the memory controller may compare the amount of write data with the predetermined threshold and cache the LBA and PA in the random cache, at 213, when the amount of write data is less than the predetermined threshold).
Regarding claim 10, Luo et al. further disclose:
The storage device of claim 1, wherein the controller determines that the host workload is a long-range random read workload (FIG. 2 step 207 Process read request), triggers a second state based on the host workload and enables updates to the cache address table (FIG. 4 step 447 Sense and transmit read data using PA of table cache).
Regarding claim 12, Luo et al. disclose:
A storage device (FIG. 1 Memory Device 110) to improve random write processing and performance on the storage device (Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device), the storage device comprises:
a persistent memory to store a logical-to-physical (L2P) table that includes a mapping of logical block addresses in a host command to physical addresses on the persistent memory (FIG. 1 L2P table 161 stored in 3D NAND; [0025] a memory array 120 including, for example, one or more individual memory die (e.g., a stack of three-dimensional (3D) NAND die)… one or more memory die of the memory array 120 can include a first complete L2P table 161 for mapping logical block addresses (LBAs) of the host with physical addresses (PAs) of the flash memory. In certain examples, the table can store the physical address and can be indexed by the logical block address to conserve storage space);
a volatile memory ([0014] Translation tables are generally loaded into an internal memory of the controller…internal memory (e.g., in random access memory (RAM)) including a cache address table to store msets in the L2P table (FIG. 1 Table Cache 130; [0033] the memory controller 115 can include a table cache 130 for storing a portion of the FTL table 161 stored on the die of the memory array) and a ulayer to store updates to msets in the L2P table (FIG. 1 Random Cache 131; [0033] the memory controller 115 can include a random cache 131…the random cache can store mapping information of write requests that have a relatively small amount of non-sequential write data); and
a controller (FIG. 1 Memory Controller 115) to receive a command (FIG. 2 step 203 Receive memory access request from host), track a set of incoming host commands to determine a host workload (FIG. 2 step 205 Read or write request?), trigger a first state on the storage device based on a first host workload (FIG. 2 step 211Write data to memory array), disable interaction with the cache address table ([0033] the random cache eliminates the need to replace the FTL table cache with mapping information associated with each LBA of each non-sequential write operation) and update the ulayer with mapping information in the host command while the storage device is in the first state (FIG. 2 step 213 Cache LBA and PA in random cache), and trigger a second state on the storage device based on a second host workload (FIG. 2 step 207 Process read request) and enable interaction with the cache address table (FIG. 1 Table Cache 130) while the storage device is in the second state (FIG. 4 step 447 Sense and transmit read data using PA of table cache).
Regarding claim 13, Luo et al. disclose:
A method for improving random write processing and performance on a storage device (Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device), the storage device (FIG. 1 Memory Device 110) comprises a controller (FIG. 1 Memory Controller 115) to execute the method comprising:
receiving host commands (FIG. 2 step 203 Receive memory access request from host);
tracking a set of incoming host commands to determine a host workload (FIG. 2 step 205 Read or write request?)
triggering a first state on the storage device based on a first host workload (FIG. 2 step 211 Write data to memory array); and
disabling interaction with a cache address table ([0033] the random cache eliminates the need to replace the FTL table cache with mapping information associated with each LBA of each non-sequential write operation) and updating a ulayer with mapping information in the host command while the storage device is in the first state (FIG. 2 step 213 Cache LBA and PA in random cache).
Regarding claim 16, Luo et al. further disclose:
The method of claim 13, further comprising tracking the set of incoming host commands to determine that the host workload is a non-long-range random write workload and switching to a second state ([0038] when the amount of write data associated with the write access command is larger than a predetermined threshold, the mapping information associated with the write access request and subsequent programming operation can be processed and saved in the table cache or the complete L2P table of the memory array according to conventional methods. As such, the memory controller may compare the amount of write data with the predetermined threshold and cache the LBA and PA in the random cache, at 213, when the amount of write data is less than the predetermined threshold).
Regarding claim 18, Luo et al. further disclose:
The method of claim 13, further comprising triggering a second state based on the host workload and enabling updates to the cache address table ([0038] when the amount of write data associated with the write access command is larger than a predetermined threshold, the mapping information associated with the write access request and subsequent programming operation can be processed and saved in the table cache or the complete L2P table of the memory array according to conventional methods. As such, the memory controller may compare the amount of write data with the predetermined threshold and cache the LBA and PA in the random cache, at 213, when the amount of write data is less than the predetermined threshold).
Regarding claim 19, Luo et al. further disclose:
The method of claim 13, further comprising determining that the host workload is a long-range random read workload (FIG. 2 step 207 Process read request), triggering a second state based on the host workload, and enabling updates to the cache address table (FIG. 4 step 447 Sense and transmit read data using PA of table cache).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 11, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. as applied to claim 1 above, and further in view of Malakar et al. (US 2025/0342113).
Regarding claim 3, Luo et al. further disclose:
The storage device of claim 1, wherein the controller flushes msets in the cache address table (FIG. 1 Table Cache 130) to the persistent memory…when the storage device enters the first state (FIG. 3 step 333 Save table cache to memory array).
Luo et al. do not appear to explicitly teach “and invalidates mset mappings in the cache address table.” However, Malakar et al. disclose:
and invalidates mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
Luo et al. and Malakar et al. are analogous art because Luo et al. teach techniques for implementing a translation cache for random access memory events and Malakar et al. teach address translation tables for improving random access performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Luo et al. and Malakar et al. before him/her, to modify the teachings of Luo et al. with the teachings of Malakar et al.
Regarding claim 5, Luo et al. further disclose:
The storage device of claim 4, wherein the controller flushes msets in the cache address table (FIG. 1 Table Cache 130) to the persistent memory…while the storage device is in the first state (FIG. 3 step 333 Save table cache to memory array).
Luo et al. do not appear to explicitly teach “and invalidates mset mappings in the cache address table.” However, Malakar et al. disclose:
and invalidates mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
The motivation for combining is based on the same rational presented for rejection of claim 3.
Regarding claim 11, Luo et al. further disclose:
The storage device of claim 1, wherein the controller flushes contents in the cache address table (FIG. 1 Table Cache 130) to the persistent memory (FIG. 3 step 333 Save table cache to memory array)…when the storage device enters the first state to maintain a chronology of L2P updates ([0042] the table cache is saved to the complete L2P table in the memory array).
Luo et al. do not appear to explicitly teach “and invalidates mset mappings in the cache address table” However, Malakar et al. disclose:
and invalidates mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
The motivation for combining is based on the same rational presented for rejection of claim 3.
Regarding claim 14, Luo et al. further disclose:
The method of claim 13, further comprising flushing msets in the cache address table to a persistent memory…when the storage device enters the first state (FIG. 3 step 333 Save table cache to memory array).
Luo et al. do not appear to explicitly teach “invalidating mset mappings in the cache address table.” However, Malakar et al. disclose:
and invalidating mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
The motivation for combining is based on the same rational presented for rejection of claim 3.
Regarding claim 15, Luo et al. further disclose:
The method of claim 13, further comprising using slots in the cache address table for consolidation of the ulayer while the storage device is in the first state (FIG. 3 step 327 Update PA in table cache), flushing msets in the cache address table to a persistent memory…while the storage device is in the first state (FIG. 3 step 333 Save table cache to memory array).
Luo et al. do not appear to explicitly teach “invalidating mset mappings in the cache address table.” However, Malakar et al. disclose:
and invalidating mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
The motivation for combining is based on the same rational presented for rejection of claim 3.
Regarding claim 20, Luo et al. further disclose:
The method of claim 13, further comprising maintaining a chronology of L2P updates by flushing contents in the cache address table to a persistent…while the storage device is in the first state (FIG. 3 step 333 Save table cache to memory array; [0042] the table cache is saved to the complete L2P table in the memory array).
Luo et al. do not appear to explicitly teach “and invalidating mset mappings in the cache address table.” However, Malakar et al. disclose:
and invalidating mset mappings in the cache address table ([0069] all L2P entries corresponding to the L2P Table N are invalidated or deleted/flushed out of the journal repository buffer 134 (corresponding to Table Cache of Luo et al.))
The motivation for combining is based on the same rational presented for rejection of claim 3.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. as applied to claim 1 above, and further in view of Wu et al. (US 2024/0201860).
Regarding claim 8, Luo et al. do not appear to explicitly teach while Wu et al. disclose:
The storage device of claim 1, wherein the controller switches to a second state when the storage device enters one of an idle state and a low power mode ([0074] during a duration (e.g., an idle duration: a duration when the memory system 302 has bandwidth to update the L2P table), the portion of the L2P table stored to the mapping merge buffer 313 (corresponds to Luo et al. table cache) may be updated).
Luo et al. and Wu et al. are analogous art because Luo et al. teach techniques for implementing a translation cache for random access memory events and Wu et al. teach address mapping for random access operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Luo et al. and Wu et al. before him/her, to modify the teachings of Luo et al. with the teachings of Wu et al. because switching to a second state that updates the L2P table with the contents of the merge buffer (table cache) during an idle period would ensure that normal memory access operations are not negatively impacted.
Regarding claim 17, Luo et al. do not appear to explicitly teach while Wu et al. disclose:
The method of claim 13, further comprising switching to a second state when the storage device enters one of an idle state and a low power mode ([0074] during a duration (e.g., an idle duration: a duration when the memory system 302 has bandwidth to update the L2P table), the portion of the L2P table stored to the mapping merge buffer 313 (corresponds to Luo et al. table cache) may be updated).
The motivation for combining is based on the same rational presented for rejection of claim 8.
Response to Arguments
Applicant's arguments filed July 21, 2026 have been fully considered but they are not persuasive.
Applicant’s remarks have been fully considered. However, the arguments with respect to the rejection of claim 1 under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the applicant regards as the invention are found unpersuasive.
Regarding the substance of the examiner’s indefiniteness rejection as argued on page 8 of the remarks, the requirements for definiteness are discussed in MPEP § 2173.02 and MPEP § 2173.05.
Applicant’s arguments regarding the indefiniteness of the terms “ulayer” and “msets” are not persuasive. Specifically, the specification does not provide an explicit definition of the terms. Applicant has provided no standard for measuring the scope of the term; an “objective standard must be provided in order to allow the public to determine the scope of the claim. A claim that requires the exercise of subjective judgment without restriction may render the claim indefinite.” See MPEP § 2173.05(b)(IV). As noted above, if applicant intends to recite the terms “ulayer” and “msets” as abbreviations, then the first occurrence of the abbreviation should accompany the non-abbreviated term.
It is noted that applicant’s remarks are only partially responsive to the 35 U.S.C. 112(b) rejections set forth in the Non-Final office action. Applicant should address all of the 35 U.S.C. 112(b) rejections as discussed above.
Therefore, the rejection of claims 1-20 as being indefinite is maintained.
Applicant’s remarks have been fully considered. However, the rejection of claims 1, 2, 4, 6-7, 9-10, 12, 13, 16, and 18-19 under 35 U.S.C. 102(a)(1) as unpatentable over Luo et al. is determined to be proper and is, therefore, maintained.
Regarding the substance of the examiner’s anticipation rejection as argued on pages 9-10 of the remarks, the requirements for anticipation are discussed in MPEP § 2131, the requirements for giving claims their broadest reasonable interpretation in lights of the specification are discussed in MPEP § 2111, and the requirements for determining the plain meaning of a terms are discussed in MPEP § 2111.01.
Based on the broadest reasonable interpretation of “trigger a first state on the storage device based on a first host workload,” receiving an access request from the host to read or writing data and writing the data to the memory array reads on the claim limitation.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., disabling interactions with a table cache 130…while the storage device is in a first state, Remarks page 10) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claim merely requires “disable interaction with the cache address table.”
The rejection of claims 1, 2, 4, 6-7, 9-10, 12, 13, 16, and 18-19 as anticipated over Luo et al. is therefore maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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