Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-10, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JANG (US 2023/0333749).
As per claim 1, Jang teaches a memory array (paragraph 7, “cell array”) that comprises an error correction circuit configured to detect if there is an error in information stored in the memory array (Fig. 2, item 251; paragraph 41, “error correction circuit may correct error in data DATA’ in cell array”, correct error can mean “detecting error in DATA’ then correcting the detected error”), wherein a location of the information within the memory array is specified by one or more addresses (paragraph 17, “arrays simultaneously accessible by a single column address”); and an off-lining logic circuit configured to determine a portion of the array based on the one or more addresses, determine if the portion is an off-lining candidate based, in part on a number of errors detected in the portion (Fig. 1, item 117; paragraph 30, "memory controller may do off-line a bad region that meets condition among bad regions of information which is received from memory 120"), and provide off-lining candidate address information associated with the portion if the portion is an off-lining candidate (Fig. 2, item 267; paragraph 48 “The information of the off-lined regions may be stored in the off-lined region storing circuit 267 of the memory 120.”).
As per claim 2, Jang teaches the off-lining logic circuit is further configured to update a count value associated with the portion and determine that the portion is an off-lining candidate if the count value crosses a threshold (paragraph 46, "The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value").
As per claim 3, Jang teaches the error correction circuit is configured to provide error correct and scrub (ECS) information (paragraph 43, “error check operation control circuit may control an error check and scrub operation”) which includes a quantity of errors detected in the location within the memory array (paragraph 43, “it may mean an operation of selecting a region with many errors”), and wherein the off-lining logic circuit is configured to update the count value by an amount based on the quantity of errors (paragraph 46, “The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value. In this case, the region stored in the error log circuit 265 may be classified as a bad region”).
As per claim 4, Jang teaches the one or more addresses includes a row address, column address, bank address, or combinations thereof (paragraphs 10, 17, 40, "row address, column address, address of off-lined region”), and wherein the portion is a section of the memory, a column plane of the memory array or a combination thereof (paragraph 45, “each region of cell array”).
As per claim 5, Jang teaches the off-lining logic circuit is further configured to write off-lining candidate address information to a mode register, a serial presence detect (SPD) chip, or both (paragraph 45, "error counting circuit may count number of errors that are detected", paragraph 46, "error log circuit may process and store counting result from error counting circuit").
As per claim 9, Jang teaches a method comprising: detecting an error associated with an address (Fig. 2, item 251; paragraph 41, “error correction circuit may correct error in data DATA’ in cell array”, correct error can mean “detecting error in DATA’ then correcting the detected error”, paragraph 17, “arrays simultaneously accessible by a single column address”), updating a count value with an off-lining logging circuit of a memory device, wherein the count value is associated with a portion of the array which includes the address (paragraph 46, “The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value”), determining if the count value has cross a threshold (paragraph 46, “The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value”), and identifying the portion of the array as a candidate for off-lining (paragraph 46, “The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value. In this case, the region stored in the error log circuit 265 may be classified as a bad region").
As per claim 10, Jang teaches detecting a quantity of errors associated with the address as part of error correct and scrub (ECS) information (paragraph 9, "number of detected errors is equal to or greater than threshold value as a result of error check and scrub operation") and updating the count value by an amount based on the quantity of errors (paragraph 46, “The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value.”)
As per claim 14, Jang teaches the generating of an off-lining candidate address information based on the identified portion. (paragraph 9, "generate information on the off-lined region")
As per claim 15, Jang teaches the storing of an off-lining candidate address information (paragraph 45, "error counting circuit may count number of errors that are detected", paragraph 46, "error log circuit may process and store counting result from error counting circuit").
As per claim 16, Jang teaches the off-lining the identified portion with a host of the memory device (Fig. 1, item 110 can be treated as the host device, paragraph 30, "memory controller may do off-line a bad region that meets condition among bad regions of information which is received from memory 120").
As per claim 17, Jang teaches a system comprising of a memory device that is comprised of a memory array (paragraph 7, “cell array”), an error correction circuit configured to detect if there is an error in information stored in the memory array (Fig.2, item 251; paragraph 41, “error correction circuit may correct error in data DATA’ in cell array”, correct error can mean “detecting error in DATA’ then correcting it”), wherein a location of the information within the memory array is specified by one or more addresses (paragraph 17, “arrays simultaneously accessible by a single column address”), an off-lining logic circuit configured to determine a portion of the array based on the one or more addresses, determine if the portion is an off-lining candidate based, in part on a number of errors detected in the portion (Fig. 1, item 117; paragraph 30, "memory controller may do off-line a bad region that meets condition among bad regions of information which is received from memory 120"), and provide off-lining candidate address information associated with the portion if the portion is an off-lining candidate (Fig. 2, item 267; paragraph 48 “The information of the off-lined regions may be stored in the off-lined region storing circuit 267 of the memory 120.”), and a host device configured to off-line the portion based on the off-lining candidate address information (Fig. 1, item 110 can be treated as the host device; paragraph 30, "memory controller may do off-line a bad region that meets condition among bad regions of information which is received from memory 120").
As per claim 18, Jang teaches a memory device being further comprising a mode register configured to store the off-lining candidate address information (paragraph 45, "error counting circuit may count number of errors that are detected", paragraph 46, "error log circuit may process and store counting result from error counting circuit"), and the host device is configured to read the off-lining candidate address information from the mode register (paragraph 46, "bad region information stored in error log circuit may be transferred to the memory controller").
As per claim 19, Jang teaches the host device comprising an access logic circuit configured to not read from or write to the off-lined portion of the memory array (paragraph 30, "memory controller may do off-line a bad region” (identify region in order not to access region there thereafter); “may not access the off-lined region")
As per claim 20, Jang teaches the off-lining logic circuit is further configured to update a count value associated with the portion and determine that the portion is an off-lining candidate if the count value crosses a threshold (paragraph 46, "The error log circuit 265 may store information of a region in which the number of errors counted by the error counting circuit 263 is equal to or greater than a threshold value. In this case, the region stored in the error log circuit 265 may be classified as a bad region.").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over JANG (US 2023/0333749) in view of FUJIWARA (US 2023/0020753).
As per claim 6, Jang teaches all the elements stated in claim 1. Jang further teaches an error tracking circuit configured to update a count value associated with the portion address and determine if the count value crosses a threshold (paragraph 45, “error counting circuit may count number of errors that are detected”, paragraph 46, “The error log circuit may store information of a region in which the number of errors counted by the error counting circuit is equal to or greater than a threshold value”). Jang does not disclose a masking circuit configured to mask the one or more addresses to determine a portion address and an address generator circuit configured to generate the off-lining candidate address information based on the portion address if the count value crosses the threshold.
However, Fujiwara discloses in a refresh address system a masking circuit may be programmed with a selected address, in which the selected address may represent an address of a defective word line (paragraph 14). Fujiwara also discloses within the same system the implementation of a refresh address generator, which may provide refresh addresses, which these addresses may correspond to a victim address, which are addresses that require refreshing (paragraph 39). This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to include a masking circuit and address generator in combination with the error tracking circuit as they can prevent the activation of defective word line regions associated with the selected address (Fujiwara, paragraph 32).
As per claim 11, Jang teaches all the elements stated in claim 9, but does not disclose the method further comprising to mask an address to determine the portion.
However, Fujiwara discloses a masking circuit may be programmed to mask a selected address, which may represent a defective word line. This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to have the masking circuit include this capability as this can prevent the activation of defective word line regions associated with the selected address (Fujiwara, paragraph 32).
As per claim 12, Jang does not disclose the method further comprising the masking a row address to determine a section as the portion, masking a column address to determine a column plane as the portion, or combinations thereof.
However, Fujiwara discloses that alongside the masking circuit may be programmed to mask a selected address (paragraph 14), the address can be in a word line (row) or a bit line (column). This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to have the masking circuit include this capability as this can prevent the activation of defective word line regions associated with the selected address (Fujiwara, paragraph 32).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of JANG (US 2023/0333749) and FUJIWARA (US 2023/0020753), in view of PELLEY (US 2015/0242269).
As per claim 7, Jang, in view of Fujiwara, does not disclose an error tracking circuit including a content addressable memory (CAM) register configured to store a plurality of portion addresses and a plurality of count values each associated with a respective one of the plurality of portion addresses.
However, Pelley discloses an inclusion of a CAM, which is responsible for holding replacement address and data of failures (paragraph 14). The CAM address entries get compared to a threshold or prefilled count value set by the CAM to determine if there is enough space to store the data in the CAM (paragraph 17). This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to include a CAM register to extend the life and reliability of the memory system and have an extra resource to replace memory that have found to be defective (Pelley, paragraph 9).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of JANG (US 2023/0333749), FUJIWARA (US 2023/0020753) and PELLEY (US 2015/0242269), in view of NAKAMURA (US 2017/0162253).
As per claim 8, Jang, in views of both Fujiwara and Pelley, do not disclose the error tracking circuit being configured to compare the portion address from the masking circuit to the stored plurality of portion addresses and if there is a match update the associated one of the plurality of count values and if there is not a match store the portion address.
However, Nakamura discloses in a refresh address system a mask determination circuit may have a comparison circuit to compare addresses received from register circuit and mask information storage circuit (paragraph 48). The comparison circuit provides an active match signal when segments between the mask and register match (paragraph 48) and a refresh operation might occur if no match happens (paragraph 26), which keeps the addresses in the register circuit. This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to include more functionality for the error tracking circuit to compare addresses between a masking circuit and stored addresses as this causes the average consumption and distribution of current in the memory device to stay consistent (Nakamura, paragraph 34).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over JANG (US 2023/0333749) in view of PELLEY (US 2015/0242269).
As per claim 13, Jang does not disclose the method further comprising of comparing a portion address associated with the portion to a plurality of stored portion addresses in a content addressable memory (CAM) register, determining if the portion address matches one of the plurality of stored portion addresses, updating a stored count value associated with a matching one of the plurality of stored portion addresses, and storing the portion address in the CAM register if there is not a matching one of the plurality of stored portion addresses.
However, Pelley discloses that the CAM entries are compared to a threshold or pre-filled count value, for which a logic circuit determines if there is space in the CAM for storing the corrected data (paragraph 17). If the initial data read by the system determines there is no correspondence with data that’s in the CAM by comparison, the data gets sent to the CAM as a CAM entry for further correction (paragraph 16). A pointer can be used to indicate the next CAM entry and update any required status bits (paragraph 22). This would have been obvious for a person having ordinary skill in the art at the time the invention was effectively filed to include of method of storing portions into a CAM register as this extends the life and reliability of the memory system and provides an extra resource to replace memory that have found to be defective (Pelley, paragraph 9). The matching also prevents the CAM from having any potential overflow from happening (Pelley, paragraph 17).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ayyapureddi (US 2024/0248796) discloses systems and methods for error scrubbing, where an error correction circuit detects memory error in a memory array and the error check and scrub circuit corrects these errors.
Li (US 2008/0307270) discloses an apparatus and method for treating memory block errors and subsequently “retiring” them when the memory blocks are marked as bad based on its history of errors.
Seshadri (US10243590) discloses detecting errors in ternary content addressable memory (TCAM), where a detection error correction code may be generated to cover complete error detection for single and double errors in TCAM entries. Each entry in the TCAM may be checked by the code for correction purposes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHANG HUU NGUYEN whose telephone number is (571)270-5978. The examiner can normally be reached Monday-Friday (8:00am - 5:00pm) ET.
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/KHANG HUU NGUYEN/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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