DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 10 and 18 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8 – 14, 17 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Machnicki et al. (US Patent Application Publication No. 2014/0237276 A1, hereinafter “Machnicki”).
As per claim 1, Machnicki teaches an apparatus,
a processor circuit [IC 10, fig. 1] including a plurality of circuit blocks [functional block(s) 15, fig. 1, 0018: IC 10 includes a number of functional blocks 15. Each of the functional blocks 15 may be one of a number of different types of functional units, and may provide different functionality from at least some of the other functional blocks 15. For example, a number of processor cores, one or more graphics processors] ; and
a power management circuit [power management unit 18, 0021: Power management unit 18 may perform various actions to control the consumption of power by IC 10. Such functions include causing the clock gating of idle functional blocks and causing power gating of idle functional blocks.] configured to:
determine a workload demand for one or more of the plurality of circuit blocks [workload allocation, 0026: each local power manager 21 is coupled to exchange various signals with power management unit 18. Each local power manager 21 may exchange performance information with power management unit 18 via a performance bus (coupled to the `Performance ‘input/output of power management unit 18). More particularly, each local power manager 21 may provide local performance information to power management unit 18, which may in turn provide global performance information to each local power manager 21; 0027: the performance information exchanged between the local power managers 21 and power management unit 18 may be used for workload allocation ]; and
in response to a determination that the workload demand is less than a threshold level:
change a performance state of the processor circuit from a first performance state [normal operation] of a plurality of performance states to a second performance state [at least one functional block is idle, 0028, 0031: The local power manager 21 of the requesting functional block 15 may detect the assertion of the clock gating signal and may respond by gating the domain clock provided thereto via domain clock gater 27. When local power manager 21 locally performs clock gating, circuitry internal to its corresponding functional block 15 is inhibited from receiving the clock signal, and thus dynamic power savings may be achieved. ] of the plurality of performance states, wherein an amount of power consumed by the processor circuit operating in the second performance state is less than the amount of power consumed by the processor circuit operating in the first performance state [0026 – 0028: Prior to asserting a request to enter a low power state, a given one of the functional blocks 15 may perform a handshaking routine with its logically adjacent neighbor(s). This may ensure that functional block 15 requesting to be placed in a low power state is not the target of a transaction from a logically adjacent functional block 15. For example, if functional block 15A is idle and intends to initiate a request to be placed in a low power state, it may first perform a handshake routine with functional block 15B to ensure that the latter does not have any pending transactions that would require the former to be available. After receiving acknowledgement from functional block 15B that there are no pending communications therefrom, functional block 15A may assert the request to be placed in a low power state; 0030: If a functional block 15 has asserted a request to be placed in a low power state and is not involved in any pending transactions, power management unit 18 may thus allow the low power state to be entered…functional blocks may be clock gated independently of each other]; and
activate a first operational mode [clock gated, 0045] in at least one circuit block of the plurality of circuit blocks, wherein the first operational mode is based on a timing margin associated with the second performance state [0030, 0045: Clock gating and power gating may be requested by control logic 220 based on determining whether functional block logic 155 and physical interface 23 have been idle for various amounts of time. In the embodiment shown, timers 218 include at least two different timers. A first of these timers is implemented for determining if a selected timeout threshold for clock gating has elapsed. A second of these timers is implemented for determining if a selected timeout threshold for power gating has elapsed.].
As per claim 2, Machnicki teaches the apparatus of claim 1, wherein, to activate a first operational mode, the power management circuit is further configured to cause clock-gating of
the at least one circuit block of the plurality of circuit blocks [0030: power management unit 18
may respond to a request by afunctional block 15 to enter a low power state by asserting a clock gating signal (`Gate Clk`).].
As per claim 3, Machnicki teaches the apparatus of claim 2, further comprising one or more clock-gating circuits configured to perform the clock-gating of the at least one circuit block of the plurality of circuit blocks, wherein a given one of the one or more clock-gating circuit comprises one or more logic gates [0030: It is noted that each of the functional blocks 15A-15D may receive a corresponding clock gating signal from power management unit 18 independently of the other functional blocks; domain clock gater 27 ].
As per claim 4, Machnicki teaches the apparatus of claim 2, wherein the power management circuit includes a storage element configured to store information indicative of which ones of plurality of circuit blocks is available for clock-gating when operating in the second performance state [0026: power management unit 18 may include a number of registers for storing the information received from the local power managers 21; 0040: Parameter registers in the embodiment shown may store parameter information for various tunable parameters that may be selected and/or set by control logic 220. In this particular embodiment, the selectable parameters include an operating voltage, and operating frequency, and timeout periods for determining when to request entry into a clock gated state and when to request entry into a low power state. It is noted however that other parameters may also be selectable and set by control logic 220 ].
As per claim 5, Machnicki teaches the apparatus of claim 2, wherein the power management circuit further includes one or more activity monitoring circuits configured to monitor respective activity levels for one or more of the plurality of circuit blocks, wherein the power management circuit is configured to activate the first operational mode based on an activity level detected by a particular one of the one or more activity monitoring circuits [local power manager 21, 0025: Each local power manager 21 may also monitor activity within its respective one of functional blocks 15A-15D ].
As per claim 8, Machnicki teaches the apparatus of claim 1, wherein a given one of the plurality of performance states is defined by a combination of a supply voltage and a clock frequency, where the combination is unique with respect to other ones of the plurality of performance states [0043 – 0044: control logic 220 may cause clock control unit to set a frequency of an operating clock signal provided to functional block 155, or to gate the operating clock signal. Setting the frequency of the operating clock signal may be based on information read from a corresponding one of parameter registers 212. For example, if the power management unit 18 indicates that IC 10 is in a high performance state and/or functional block 155 is performing a heavy workload, control logic 220 may cause clock control unit 214 to set the operating clock to a high frequency…. Control logic 220 may cause voltage control unit 216 to set the operating voltage based on information red from parameter registers 212 responsive to receiving global performance information from power management unit 18. If higher performance is desired, the operating voltage may be set to a higher level commensurate with the performance demands.].
As per claim 9, Machnicki teaches the apparatus of claim 8, wherein the processor circuit is configured to operate at a first clock frequency when operating in the first performance state, and wherein the processor circuit is further configured to operate at a second clock frequency when operating in the second performance state, wherein the second clock frequency is less than the first clock frequency [0043: control logic 220 may cause clock control unit to set a frequency of an operating clock signal provided to functional block 155, or to gate the operating clock signal. Setting the frequency of the operating clock signal may be based on information read from a corresponding one of parameter registers 212…if power management unit 18 indicates that IC 10 is in a low performance state, or if functional block 155 is performing a light workload, control logic 220 may cause clock control unit 214 to reduce the operating clock frequency.].
As per claim 10, it is directed to the method of steps to implement on the apparatus set forth in claims 1. Machnicki teaches the claimed apparatus. Therefore, Machnicki teaches the method to implement the claims steps.
As per claim 18, it is directed to the system to implement with the apparatus set forth in claims 1. Machnicki teaches the claimed apparatus. Therefore, Machnicki teaches the system to implement the apparatus.
As per claim 11, Machnicki teaches the method of claim 10, wherein activating the first operational mode comprises, based on the timing margin associated with the second one of the plurality of performance states, clock-gating of the at least one circuit block using one or more clock-gating circuits implemented within the at least one circuit block [0030, 0045: Clock gating and power gating may be requested by control logic 220 based on determining whether functional block logic 155 and physical interface 23 have been idle for various amounts of time. In the embodiment shown, timers 218 include at least two different timers. A first of these timers is implemented for determining if a selected timeout threshold for clock gating has elapsed. A second of these timers is implemented for determining if a selected timeout threshold for power gating has elapsed.].
As per claim 12, Machnicki teaches the method of claim 11, further comprising storing, in a storage element of the power management circuit, information indicative of which ones of the plurality of circuit blocks is available for clock-gating when operating in the second one of the plurality of performance states [0026: power management unit 18 may include a number of registers for storing the information received from the local power managers 21; 0040: Parameter registers in the embodiment shown may store parameter information for various tunable parameters that may be selected and/or set by control logic 220. In this particular embodiment, the selectable parameters include an operating voltage, and operating frequency, and timeout periods for determining when to request entry into a clock gated state and when to request entry into a low power state. It is noted however that other parameters may also be selectable and set by control logic 220 ].
As per claim 13, Machnicki teach the method of claim 11, further comprising monitoring, using one or more activity monitoring circuits implemented in the power management circuit, respective activity levels for one or more of the plurality of circuit blocks [local power manager 21, 0025: Each local power manager 21 may also monitor activity within its respective one of functional blocks 15A-15D ].
As per claim 14, Machnicki teaches the method of claim 13, further comprising activating, using the power management circuit, clock-gating based on an activity level detected by a particular one of the one or more activity monitoring circuits [local power manager 21, 0025: Each local power manager 21 may also monitor activity within its respective one of functional blocks 15A-15D ].
As per claim 17, Machnicki teaches the method of claim 10, wherein operating in the first one of the plurality of performance states comprises operating the processor circuit at a first clock frequency and operating the second one of the plurality of performance states comprises operating the processor circuit at a second clock frequency that is less than the first clock frequency [0043: control logic 220 may cause clock control unit to set a frequency of an operating clock signal provided to functional block 155, or to gate the operating clock signal. Setting the frequency of the operating clock signal may be based on information read from a corresponding one of parameter registers 212…if power management unit 18 indicates that IC 10 is in a low performance state, or if functional block 155 is performing a light workload, control logic 220 may cause clock control unit 214 to reduce the operating clock frequency.]..
As per claim 19, Machnicki teaches the system of claim 18, wherein the power management circuit includes a configured to store information indicative of which ones of the plurality of circuit blocks is available for clock-gating when operating in the second performance state [0026: power management unit 18 may include a number of registers for storing the information received from the local power managers 21; 0040: Parameter registers in the embodiment shown may store parameter information for various tunable parameters that may be selected and/or set by control logic 220. In this particular embodiment, the selectable parameters include an operating voltage, and operating frequency, and timeout periods for determining when to request entry into a clock gated state and when to request entry into a low power state. It is noted however that other parameters may also be selectable and set by control logic 220 ].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 15, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Machnicki et al. (US Patent Application Publication No. 2014/0237276 A1, hereinafter “Machnicki”), in view of Elappuparackal (US Patent Application Publication No. 2004/0239367).
As per claim 6, Machnicki teaches the apparatus of claim 2. However, Machnicki does not teach “…wherein at least one of the plurality of circuit blocks includes at least exclusive-OR clock-gating circuit configured to, when the processor circuit is operating in the second performance state, determine if a respective states of an input and an output of a correspondingly coupled sequential circuit has changed, and, in response to a determination that the respective states of the input and the output of the correspondingly coupled sequential circuit has not change, perform clock-gating of the correspondingly coupled sequential circuit…”.
Elappuparackal teaches a fine grain XOR data-driven gating scheme that gates registers whose data has not changed. Elappuparackal improves Machnicki by allowing the functional blocks to clock gate while assigned a light workload, as Machnicki’s invention clock gates only after a block has been idle passed a timeout. Both Elappuparackal and Machnicki are directed toward dynamic clock power in processors.
As per claim 6, Elappuparackal further teaches … wherein at least one of the plurality of circuit blocks includes at least exclusive-OR clock-gating circuit configured to, when the processor circuit is operating in the second performance state, determine if a respective states of an input and an output of a correspondingly coupled sequential circuit has changed, and, in response to a determination that the respective states of the input and the output of the correspondingly coupled sequential circuit has not change, perform clock-gating of the correspondingly coupled sequential circuit [flip-flop is clocked only when its input differs from the data it holds; bit groups can each have their own GCLK, 0015 – 0016, 0030-0038, 0041 - 0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Elappuparackal and Machnicki, as Elappuparackal explicitly teaches other clock gating and hence, power saving opportunities.
As per claim 151, Elappuparackal teaches The method of claim 11, further comprising clock-gating a first sequential circuit in in the at least one circuit block by comparing, using an exclusive-OR gate, an input of the first sequential circuit to an output of the first sequential circuit [fig. 5, XOR 140 -143, 0041 - 0046].
As per claim 16, Elappuparackal teaches the method of claim 15, further comprising clock-gating a plurality of sequential circuits, including the first sequential circuit by comparing, using corresponding ones of a plurality of exclusive-OR gates, respective inputs to respective outputs of ones of the plurality of sequential circuits and logically ORing respective outputs of the plurality of exclusive-OR gates to generate a clock-gating term [flip-flop is clocked only when its input differs from the data it holds; bit groups can each have their own GCLK, 0015 – 0016, 0030-0038, 0041 - 0046].
As per claim 20, Elappuparackal teaches the system of claim 18, wherein the at least one circuit block of the plurality of circuit blocks includes at least exclusive-OR clock-gating circuit configured to, when the processor circuit is operating in the second performance state, determine if a respective states of an input and an output of a correspondingly coupled sequential circuit has changed, and, in response to a determination that the respective states of the input and the output of the correspondingly coupled sequential circuit has not change, perform clock gating of the correspondingly coupled sequential circuit [flip-flop is clocked only when its input differs from the data it holds; bit groups can each have their own GCLK, 0015 – 0016, 0030-0038, 0041 - 0046].
Allowable Subject Matter
Claim objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kazachinsky et al. (US Patent Application Publication No. 2006/0129860 A1) “Method And Apparatus For Reducing Clock Frequency During Low Workload Periods” is cited to teach a clock frequency control unit for an integrated circuit (IC) that includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal.
Sekiguchi; Hideyuki. (US Patent Application Publication No. 2017/0019113 A1) “Semiconductor Device And Method For Controlling The Semiconductor Device” is cited to teach a semiconductor device that includes: a clock synchronizing circuit that operates in synchronization with a clock; an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and a clock supplying circuit that supplies a clock to the clock synchronizing circuit or stop the supply of the clock according to the enable signal when a clock frequency is equal to or lower than a predetermined frequency, and supply a clock to the clock synchronizing circuit, irrespective of the enable signal, when the clock frequency is higher than the predetermined frequency.
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
1 Similar rationale as applied to claim 6 is also applied to claims 15, 16, and 20, to the extent applicable.
