DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 25th, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 and 12 objected to because of the following informalities: Claim 1 reads “writing to-be-written data into a physical word line corresponding to the physical word line group according to the physical word line group corresponding to the logical word line of each logic unit”. This is sentence is unclear and appears the additional reference of the physical word line group term is unnecessary. The examiner asserts the claim should read “writing to-be-written data into a physical word line corresponding to the physical word line group corresponding to the logical word line of each logic unit”. Claim 12 is the corresponding device claim to method claim 1 and contains the same informality.
Appropriate correction is required.
Claim Interpretation
Claims 3-7 contain explicit contingent limitations in a method claim, and outline the entire claim function as only occurring “if” a particular determination occurs. The claims are comprised of an “if…then…” statement, with no actual requirement that the determination described in the “if” statement happens. In this case, the claims are interpreted under the broadest reasonable interpretation, wherein the determination does not occur. The examiner notes that the system claims 13-18 require the structure necessary to complete the claim steps, and are therefore indicated as containing allowable subject matter, as described below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-7 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drissi et al. (US Publication No. 2025/0028484 – “Drissi”) in view of Zhou et al. (US Publication No. 2024/0061583 – “Zhou”).
Regarding claim 1, Drissi teaches A method for managing flash memory, applied to a flash memory device, comprising: acquiring a write request, wherein the write request comprises physical address information and to-be-written data; (Drissi paragraph [0012], a memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system used to store the data is stored based on the received logical address, a last logical address written at the memory system, a sequence number group associated with the last logical address, and the sequential nature of the write operations. Based on determining the physical address, the memory system may read the data stored at the physical address. Write requests for to-be-written write data can use physical address information, which may be used in the context of a flash memory system, see Drissi paragraph [0015], A memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory system 110 may be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device) looking up a mapping table (Drissi paragraph [0039], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used—e.g., when information is sequentially written to a memory device 130. A direct L2P approach may involve using information associated with accessing the memory system 110 to determine a logical-to-physical mapping. In some examples, a memory system 110 may write data to a memory device based on (e.g., in response to) receiving multiple write commands. The memory system 110 may write the data to sequential physical addresses of the memory device 130, where the sequential physical addresses may be associated with sequential logical addresses for the memory system 110. A mapping table may be used to perform specific memory functions/commands) and writing to-be-written data into a physical word line corresponding to the physical word line group according to the physical word line group corresponding to the logical word line of each logic unit (Drissi paragraph [0012], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used. A direct L2P approach may involve using information associated with accessing the memory system to determine a logical-to-physical mapping. In some examples, a memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system used to store the data is stored based on the received logical address, a last logical address written at the memory system, a sequence number group associated with the last logical address, and the sequential nature of the write operations. Based on determining the physical address, the memory system may read the data stored at the physical address. Write (and read) operations corresponding to to-be-written data to the word line based on physical/logical wordlines).
Drissi does not teach acquiring a logical word line address corresponding to each logic unit in at least one logic unit according to physical address information corresponding to the write request; according to the logical word line address corresponding to each logic unit, and determining a physical word line group corresponding to the logical word lines of each logic unit, wherein the mapping table comprises a mapping relationship between the logical word lines and the physical word line group, the physical word line group comprises at least one physical word line, numbers of data pages comprised in at least two physical word lines are not exactly the same, and each physical word line comprises a plurality of data pages.
However, Zhou teaches acquiring a logical word line address corresponding to each logic unit in at least one logic unit according to physical address information corresponding to the write request; (Zhou paragraph [0047], At operation 320, the processing logic determines that the wordline is disposed on a particular (e.g., first) deck of the memory device (e.g., a top deck or a bottom deck). In some embodiments, determining that the wordline is disposed on the first deck of the memory device can be based on identifying a physical and/or logical address of the wordline. For example, the processing logic can identify that the logical address of the wordline is WL 3. The processing logic can use a data structure, such as a mapping table, to identify a deck to which the wordline is mapped based on the address of the wordline. The data structure can list each wordline of the memory device in an entry and can list a corresponding deck of the memory device on which the wordline is disposed in an associated (e.g., linked) entry. In some embodiments, the data structure can be preconfigured at manufacturing of the memory device. In some embodiments, the data structure can be stored on the memory device. In some embodiments, the data structure can be the configuration table illustrated in FIG. 2. The memory system may utilize a physical and logical address of wordlines for a given logical unit (i.e., data structure as described above)) according to the logical word line address corresponding to each logic unit, and determining a physical word line group corresponding to the logical word lines of each logic unit, (Zhou paragraph [0047], At operation 320, the processing logic determines that the wordline is disposed on a particular (e.g., first) deck of the memory device (e.g., a top deck or a bottom deck). In some embodiments, determining that the wordline is disposed on the first deck of the memory device can be based on identifying a physical and/or logical address of the wordline. For example, the processing logic can identify that the logical address of the wordline is WL 3. The processing logic can use a data structure, such as a mapping table, to identify a deck to which the wordline is mapped based on the address of the wordline. The data structure can list each wordline of the memory device in an entry and can list a corresponding deck of the memory device on which the wordline is disposed in an associated (e.g., linked) entry. In some embodiments, the data structure can be preconfigured at manufacturing of the memory device. In some embodiments, the data structure can be stored on the memory device. In some embodiments, the data structure can be the configuration table illustrated in FIG. 2. Logical and physical word lines specifically can be mapped together) wherein the mapping table comprises a mapping relationship between the logical word lines and the physical word line group, (Zhou paragraph [0047], At operation 320, the processing logic determines that the wordline is disposed on a particular (e.g., first) deck of the memory device (e.g., a top deck or a bottom deck). In some embodiments, determining that the wordline is disposed on the first deck of the memory device can be based on identifying a physical and/or logical address of the wordline. For example, the processing logic can identify that the logical address of the wordline is WL 3. The processing logic can use a data structure, such as a mapping table, to identify a deck to which the wordline is mapped based on the address of the wordline. The data structure can list each wordline of the memory device in an entry and can list a corresponding deck of the memory device on which the wordline is disposed in an associated (e.g., linked) entry. In some embodiments, the data structure can be preconfigured at manufacturing of the memory device. In some embodiments, the data structure can be stored on the memory device. In some embodiments, the data structure can be the configuration table illustrated in FIG. 2. Logical and physical word lines specifically can be mapped together) the physical word line group comprises at least one physical word line, numbers of data pages comprised in at least two physical word lines are not exactly the same, and each physical word line comprises a plurality of data pages; (Zhou paragraph [0013], A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device in order to allow concurrent operations to take place on each plane. The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include a respective access line driver circuit and power circuit for each plane of the memory device to facilitate concurrent access of pages of two or more memory planes, including different page types. The physical word line group may include physical word lines, which can contain data pages of differing types (i.e., not the same)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Drissi with those of Zhou. Zhou teaches using a physical word line group containing word lines with differing page types, which can allow for additional flexibility in the memory sub-system and can allow determining specific parameters for specific wordlines (i.e., see Zhou paragraph [0018], Some memory devices, such as three-dimensional (3D) cross-point devices, can include multiple portions. A portion, such as a deck or layer, can be defined as a two-dimensional (2D) array of memory cells electronically addressable by a vertical access line(s). Multiple decks can be stacked within a memory device (e.g., stacked vertically). Certain memory cells of certain wordlines of each deck can inherently have differing RWBs and thus differing memory device reliability than other memory cells of other wordlines and Zhou paragraph [0019], Aspects of the present disclosure address the above and other deficiencies by implementing adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system).
Claim 12 is the corresponding device claim to method claim 1 and is rejected with the same references and rationale. Claim 9 is the corresponding method claim including a reading command as opposed to the write command described in claim 1, and is also rejected with the same references and rationale, as described explicitly in Drissi paragraph [0012], In some examples, a memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address).
Regarding claim 3, Drissi in view of Zhou teaches The method according to claim 1, wherein before acquiring a write request, the method further comprises: establishing a mapping table, comprising: if a physical block of the flash memory device comprises two types of physical word lines, namely a first physical word line and a second physical word line, then: performing a mapping starting from the physical word line with the smallest serial number; (Drissi paragraph [0039], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used—e.g., when information is sequentially written to a memory device 130. A direct L2P approach may involve using information associated with accessing the memory system 110 to determine a logical-to-physical mapping. In some examples, a memory system 110 may write data to a memory device based on (e.g., in response to) receiving multiple write commands. The memory system 110 may write the data to sequential physical addresses of the memory device 130, where the sequential physical addresses may be associated with sequential logical addresses for the memory system 110. Based on (e.g., after) writing the data to the memory device 130, the memory system 110 may receive a request for the data stored in the memory device 130, where the request may include a logical address the corresponds to the physical address of the data. The memory system 110 may determine the physical address of the data based on the received logical address, a last logical address written to by the memory system 110, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system 110 may read the data set stored at the physical address in the memory device 130. Logical word line addresses may be mapped to correlate to a physical word line group) identifying whether a current physical word line is the first physical word line; if yes, combining several consecutive first physical word lines into a first physical word line group and mapping the first physical word line group to a logical word line; if no, determining that the current physical word line is a second physical word line, and mapping the current physical word line directly to one logical word line; and traversing all physical word lines of a physical block, wherein the first physical word line comprises a first number of data pages, the second physical word line comprises a second number of data pages, the second number is greater than the first number and the number of data pages of the logical word line is less than or equal to the number of data pages of the physical word line or the physical word line group corresponding to the logical word line, and the number of data pages of the logical word line is equal to the number of data pages corresponding to the physical word line with the largest serial number.
Regarding claim 4, Drissi in view of Zhou teaches The method according to claim 3, wherein the establishing a mapping table further comprises: (Drissi paragraph [0039], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used—e.g., when information is sequentially written to a memory device 130. A direct L2P approach may involve using information associated with accessing the memory system 110 to determine a logical-to-physical mapping. In some examples, a memory system 110 may write data to a memory device based on (e.g., in response to) receiving multiple write commands. The memory system 110 may write the data to sequential physical addresses of the memory device 130, where the sequential physical addresses may be associated with sequential logical addresses for the memory system 110. Based on (e.g., after) writing the data to the memory device 130, the memory system 110 may receive a request for the data stored in the memory device 130, where the request may include a logical address the corresponds to the physical address of the data. The memory system 110 may determine the physical address of the data based on the received logical address, a last logical address written to by the memory system 110, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system 110 may read the data set stored at the physical address in the memory device 130. Logical word line addresses may be mapped to correlate to a physical word line group) if a physical block of the flash memory device comprises three types of physical word lines, namely a first physical word line, a second physical word line and a third physical word line, then: performing a mapping starting from the physical word line with the smallest serial number; identifying whether the current physical word line is the first physical word line, wherein the first physical word line comprises a first number of data pages; if yes, combining several consecutive first physical word lines into a first physical word line group and mapping the first physical word line group to a logical word line; if no, further identifying whether the current physical word line is a second physical word line, wherein the second physical word line comprises a second number of data pages, and the second number is greater than the first number; if the current physical word line is the second physical word line, combining several consecutive second physical word lines into a second physical word line group and mapping the second physical word line group to a logical word line; if the current physical word line is not the second physical word line, determining that the current physical word line is a third physical word line, and mapping the current physical word line directly to one logical word line; and traversing all physical word lines of a physical block, wherein the third physical word line comprises a third number of data pages, the third number is greater than the second number and the number of data pages of the logical word line is less than or equal to the number of data pages of the physical word line or the physical word line group corresponding to the logical word line, and the number of data pages of the logical word line is equal to the number of data pages corresponding to the physical word line with the largest serial number.
Regarding claim 5, Drissi in view of Zhou teaches The method according to claim 4, wherein the establishing a mapping table further comprises: (Drissi paragraph [0039], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used—e.g., when information is sequentially written to a memory device 130. A direct L2P approach may involve using information associated with accessing the memory system 110 to determine a logical-to-physical mapping. In some examples, a memory system 110 may write data to a memory device based on (e.g., in response to) receiving multiple write commands. The memory system 110 may write the data to sequential physical addresses of the memory device 130, where the sequential physical addresses may be associated with sequential logical addresses for the memory system 110. Based on (e.g., after) writing the data to the memory device 130, the memory system 110 may receive a request for the data stored in the memory device 130, where the request may include a logical address the corresponds to the physical address of the data. The memory system 110 may determine the physical address of the data based on the received logical address, a last logical address written to by the memory system 110, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system 110 may read the data set stored at the physical address in the memory device 130. Logical word line addresses may be mapped to correlate to a physical word line group)if a physical block of the flash memory device comprises N types of physical word lines, namely a first physical word line, a second physical word line, ... the (N-1)th physical word line and an Nth physical word line, then: if the current physical word line is not the second physical word line, continuing to identify whether the current physical word line is the third physical word line; if yes, combining several third physical word lines into one third physical word line group and mapping the one third physical word line group to one logical word line; repeating until it is identified whether the current physical word line is the (N-1)th physical word line; if the current physical word line is the (N-1)th physical word line, combining several (N-1)th physical word lines into one (N-1)th physical word line group and mapping the one (N-1)th physical word line group to one logical word line; if the current physical word line is not the (N-1)th physical word line, determining that the current physical word line is a (N-1)th physical word line, and mapping the current physical word line directly to one logical word line; and traversing all physical word lines of a physical block, wherein N is a positive integer and greater than the third number, and the number of data pages of each logical word line is the same, and the number of data pages of the logical word line is less than or equal to the number of data pages of the physical word line or physical word line group corresponding to the logical word line, the logical word lines correspond one by one to the physical word lines with the maximum number of data pages, and the number of data pages of the logical word lines is equal to the number of data pages corresponding to the physical word line with the largest serial number.
Regarding claim 6, Drissi in view of Zhou teaches The method according to claim 1, wherein the writing to-be-written data into a physical word line corresponding to the physical word line group according to the physical word line group corresponding to the logical word line of each logic unit comprises: writing data corresponding to each logic unit in the to-be-written data into the physical word line group corresponding to each logic unit in parallel, wherein: if the physical word line group corresponding to the logic unit comprises one physical word line, writing data in the to-be-written data corresponding to the logic unit into the physical word line; and if the physical word line group corresponding to the logic unit comprises at least two physical word lines, writing data in the to-be-written data corresponding to the logic unit into the at least two physical word lines (Drissi paragraph [0039], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used—e.g., when information is sequentially written to a memory device 130. A direct L2P approach may involve using information associated with accessing the memory system 110 to determine a logical-to-physical mapping. In some examples, a memory system 110 may write data to a memory device based on (e.g., in response to) receiving multiple write commands. The memory system 110 may write the data to sequential physical addresses of the memory device 130, where the sequential physical addresses may be associated with sequential logical addresses for the memory system 110. Based on (e.g., after) writing the data to the memory device 130, the memory system 110 may receive a request for the data stored in the memory device 130, where the request may include a logical address the corresponds to the physical address of the data. The memory system 110 may determine the physical address of the data based on the received logical address, a last logical address written to by the memory system 110, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system 110 may read the data set stored at the physical address in the memory device 130. Logical word line addresses may be mapped to correlate to a physical word line group with a determined number of word lines).
Regarding claim 7, Drissi in view of Zhou teaches The method according to claim 6, further comprising: if the physical word line group corresponding to the logic unit comprises one physical word line, writing data in the to-be-written data corresponding to the logic unit into the physical word line and determining that the writing is completed; (Drissi paragraph [0012], To decrease latency associated with determining L2P mappings and decrease the fatigue of memory used to store L2P mappings, a direct L2P approach may be used. A direct L2P approach may involve using information associated with accessing the memory system to determine a logical-to-physical mapping. In some examples, a memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system used to store the data is stored based on the received logical address, a last logical address written at the memory system, a sequence number group associated with the last logical address, and the sequential nature of the write operations. Based on determining the physical address, the memory system may read the data stored at the physical address. Write (and read) operations corresponding to to-be-written data to the word line based on physical/logical wordlines) and if the physical word line group corresponding to the logic unit comprises at least two physical word lines, after writing data in the to-be-written data corresponding to the logic unit into the at least two physical word lines, filling invalid data into a remaining space of the physical word line group and determining that the writing is completed, wherein a data volume of the to-be-written data is equal to the number of logic units in one die of the flash memory device multiplied by the numbers of data pages corresponding to one logic unit multiplied by a size of one data page.
Regarding claim 10, Drissi in view of Zhou teaches The method according to claim 9, wherein the reading data corresponding to a read request according to a physical word line address of the physical word line group comprises: determining a data page address corresponding to a physical word line address according to the physical word line address and reading data corresponding to the data page address (Drissi paragraph [0029], In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes 165). A data page address for a given wordline may be determined, and used for performing memory functions/operations, as described above).
Regarding claim 11, Drissi in view of Zhou teaches The method according to claim 9, wherein the logical word line address comprises a plurality of logical data pages, wherein a size of each logical data page is equal to a size of one physical data page, (Drissi paragraph [0053], At block 335, a sequence number group may be determined based on the global sequence number and a quantity of blocks (represented by N) used to contain a full set of logical addresses. In some examples, the sequence number may be determined by dividing the global sequence number by the quantity of blocks used to contain the full set of logical addresses—e.g., when the quantity of logical addresses is equivalent to the quantity of pages (which may be represented by P or SizeBlockInLBA) supported by the blocks used to contain the full set of logical addresses. In some examples, the sequence number may be determined by determining the global sequence number, a quantity of logical addresses, and a quantity of pages included in the blocks—e.g., when the quantity of logical addresses is different than the quantity of pages supported by the blocks used to contain the full set of logical addresses. The size of the logical data pages may be determined and may be equal to the physical size of pages based on the data blocks) and a starting address of a logical data page is the address of a first mapped physical word line (Drissi paragraph [0064], In some examples and as shown in FIG. 4, a last address of the quantity of logical addresses (which may be represented by K) may map to a portion of a block 405. In such cases, a repeated set of the logical addresses may begin in a non-zero starting point (e.g., a middle) of a block. In such cases, the calculation of the sequence number group 415 for which a logical address is associated may involve determine a starting location of each sequence number group 415—e.g., instead of dividing the sequence associated with a logical address by the quantity of blocks 405 used to contain the set of logical addresses. The starting address of a logical page may be determined based on sequential physical address location).
Claim(s) 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drissi in view of Zhou as applied to claims 1 and 12 above, and further in view of Bolisetty (US Publication No. 2024/0069806 – “Bolisetty”).
Regarding claim 8, Drissi in view of Zhou in further view of Bolisetty teaches The method according to claim 1, wherein the physical address information comprises an address of a die, (Bolisetty paragraph [0059], The sequential write can be performed consecutively from the top of the memory device (e.g., smaller addresses of IC die) to the bottom of the memory device (e.g., larger addresses of the IC die), which is illustrated by the patterned blocks of data already written to the illustrated zones 232A-Z. In these embodiments, the device mapping logic 228 can track block numbers (e.g., logical block addresses) of a namespace) an address of at least one logic unit, an address of a physical block, (Bolisetty paragraph [0053], For example, file system 124 can store the object metadata in an index node (“inode”) data structure and the index node data structure can have one or more pointers to the object data. The inode can be a data structure in a Unix-style file system that describes a file system object. Each inode can indicate the attributes and storage locations (e.g., block addresses) of the data of the file system object) and a logical word line address (Zhou paragraph [0047], At operation 320, the processing logic determines that the wordline is disposed on a particular (e.g., first) deck of the memory device (e.g., a top deck or a bottom deck). In some embodiments, determining that the wordline is disposed on the first deck of the memory device can be based on identifying a physical and/or logical address of the wordline)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Drissi and Zhou with those of Bolisetty. Bolisetty teaches more specific physical address information, including address information for a corresponding die, which can allow for more larger address operations/targeting and better maintaining over mapping structures (i.e., see Bolisetty paragraph [0022], for storing mapping data structures that track logical-to-physical (LTP) address mapping between logical block address (LBA) space and physical address space of the IC dies. For example, mapping overhead is about a gigabyte (GB) per terabyte (TB) of host addressable media, and thus, a 16 TB solid-state drive (SSD) requires a significant 16 GB of memory mapping overhead. Additionally, periodic snapshotting and logging is done to persist the mapping data structures across shutdowns and surprise power failure situations. This can add additional write overhead to the IC dies and performance loss).
Claim 19 is the corresponding device claim to method claim 8. It is rejected with the same references and rationale.
Allowable Subject Matter
Claims 2 and 13-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Dependent claims 2 and 13-18 have been indicated as containing allowable subject matter. Dependent claim 2 recites specific details regarding determining the number of data pages corresponding to a physical word line (comprising the physical word line group), wherein a largest serial number in a physical wordline group is equal to the number of data pages of one logical word line. Claim 13 recites similar features. Claims 14-18 recite further details regarding the mapping table that comprises the mapping relationship between the logical wordline address and the physical wordline group, comprising the physical wordlines (each of which comprises a differing number of data pages). The claims recite more specific details regarding the identification of the physical word lines, such as starting the mapping with the lowest serial number, as well as the combination of physical word lines comprising less data pages per wordline into a singular physical word line for the execution of the read/write operation as described in the independent claim. These features regarding the determination of a quantity of data pages existing in a physical word line comprising a physical word line group for a mapping relationship between logical and physical word line addresses is not taught in the technological field, and would be allowable if rewritten to be included in the independent claim. The examiner again notes that dependent claims 3-7 are not indicated as objected, as the claims feature highly contingent method claim limitations and would not overcome the existing prior art in their current form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barsky et al. (US Publication No. 2010/0257309 – Barsky) teaches determining logical page addresses based on a determined index value for mapping operations between logical and physical addresses (i.e., see Barsky paragraph [0019], The method can include accessing a first mapping data structure, a second data structure and a third data structure; wherein the first mapping data structure maps logical erase block addresses to physical erase block addresses, the second mapping data structure maps logical page addresses to indexes into the third mapping data structure; wherein the third data structure maps the indexes to locations of sets of flash memory cells; wherein at least one erasure block includes two sets of flash memory cells that differ from each other by their size).
Marcu et al. (US Publication No. 2015/0154118 – “Marcu”) teaches a method for one-to-one mapping between logical and physical word line addresses, as well as storage length determination (i.e., see Marcu paragraph [0026], Alternatively, one logical-to-physical address table may be used, but each LBA will be associated with three values: wordline address, offset address, and length. This is illustrated in FIG. 4, with LBA1 being associated with the entries 400, 45, 512. The means that LBA1 is mapped to wordline number 400, and its associated data begins at an offset of 45 bytes and is 512 bytes long. LBA2 is a not compressed; therefore, the offset is set to 0, and the length is set to 4K, which is the full length of a wordline in this example. LBA3 is mapped to the beginning of wordline 1000, although it is compressed and its physical storage length is just 256 bytes. If no compression is used and all the units are of the same size, then the size information is not needed, and the offset becomes an index of the logical unit index inside the page).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached Monday - Friday 8 AM - 5 PM.
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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