DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hussien et al. (US 2018/0284829).
Regarding claims 1 and 10, Hussien et al.’s figure 5 shows A parasitic capacitance cancellation circuit, comprising: a first transistor (MPn), comprising a first terminal (drain), a control terminal (gate electrode), and a second terminal (source); a first coupler (Cgd), configured to couple the control terminal of the first transistor and the first terminal of the first transistor; a second coupler (Cgs), configured to couple the control terminal of the first transistor and the second terminal of the first transistor; and a negative impedance generator (502), configured to generate and provide a negative impedance to the control terminal of the first transistor to cancel a parasitic capacitance of the first transistor as called for in claims 1 and 10.
Regarding claim 9, wherein the negative impedance generator comprises a capacitor (-C), and the capacitor comprises: a first terminal, configured to receive a first control signal; and a second terminal, coupled to the control terminal of the first transistor; wherein the control terminal of the first transistor is configured to receive a second control signal (Vx), wherein the negative impedance generator provides the negative impedance to the control terminal of the first transistor according to the first control signal.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 5/27/2026
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