DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is responsive to communication filed on 03/25/2025.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 15 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the specification [0046] recites that a propagated signal may be included within the scope of computer-readable storage media. Therefore, claim 15 can be a signal per se.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 - 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Koch et al (US 2010/0283505; hereinafter Koch).
Regarding claim 1, Koch discloses a dynamically reconfigurable fieldbus communications interface (abstract) comprising:
programmable logic (paragraphs [0479], [0481]; Koch discloses that a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein) that comprises a static area and at least one dynamic area (paragraph [0353]; Koch discloses that dedicated signals may be defined and constrained to be mapped to the same wires so that a static part of a system can communicate with a dynamic reconfigurable part of the system over these wires. Such wires will be used to link together the static and the dynamic part of the system among different modules placed into an area allocated for dynamically partial reconfiguration); and
control circuitry configured to program the at least one dynamic area using one of a plurality of interchangeable fieldbus stack hardware configurations (paragraphs [0333 - 0334], [0353]; Koch discloses that we assume that partially reconfigurable modules are bound to rectangular regions. This can be achieved by applying some place and route constraints to the interchangeable modules. In addition, dedicated signals may be defined and constrained to be mapped to the same wires so that a static part of a system can communicate with a dynamic reconfigurable part of the system over these wires), each conforming to a respective fieldbus protocol type (paragraph [0333]; Korch discloses that reconfiguration may be used to adapt a system to time-variant demands. For example, at daytime we may have a high demand for voice-over-IP packets in a network processing system, while later the system may adapt to some other protocols by partial reconfiguration).
Regarding claim 2, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein the at least one dynamic area is dynamically reconfigurable to operate according to a selected fieldbus protocol type without affecting the static area or any other dynamic area (paragraphs [0314]. [0328], [0333] ; Koch discloses that the following sections present techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. In contrast to other approaches, our generated buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads).
Regarding claim 3, Koch discloses dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein a size of the at least one dynamic area is determined to accommodate the largest of the interchangeable fieldbus stack hardware configurations (paragraphs [0021], [0166], [0353]; Koch discloses that we assume that partially reconfigurable modules are bound to rectangular regions. This can be achieved by applying some place and route constraints to the interchangeable modules).
Regarding claim 4, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, further comprising pin switches for the different fieldbus protocol types implemented within the at least one dynamic area (paragraphs [0047], [0068 - 0069], [0241 – 0242]; Koch discloses that the first switching matrix (comprising the bypass path) and the second switch matrix (providing access between the communication bar and the logic circuitry of the communication-bar-access resource block) are "drop-in-replacements". In other words, the first switch matrix and the second switch matrix are pin-compatible with respect to the terminals connected to the communication bar).
Regarding claim 5, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein the at least one dynamic area outputs only one set of fieldbus signals (paragraphs [0032 – 0033]).
Regarding claim 6, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 5, wherein the control circuitry is configured to receive a reconfiguration command specifying a required fieldbus protocol type and, in response to receiving the reconfiguration command (paragraphs [0048], [0081]):
to identify a target fieldbus instance to be exchanged based on the reconfiguration command (paragraphs [0048], [0081]);
to load a replacement fieldbus stack hardware configuration corresponding to the required fieldbus protocol type onto a dynamic area currently occupied by the target fieldbus instance paragraphs [0048], [0081 - 0083]);
to verify that loading of the replacement fieldbus stack hardware configuration successfully created a replacement fieldbus instance (paragraphs [0048], [0081 - 0083]; Koch discloses that in some embodiments the logic chip configuration manager is configured to dynamically change the configuration of the logic chip in response to a change of the requirements. Such a flexible resource configuration is possible due to the uniform structure of the communication bar with respect to the interface locations.);
to establish communication between the replacement fieldbus instance and at least one field device (paragraphs [0083], [0086], [0091], [0213]).
Regarding claim 7, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein the programmable logic comprises a plurality of dynamic areas including the at least one dynamic area, whereby the dynamically reconfigurable fieldbus communications interface is operable to host multiple fieldbus instances, each corresponding to a specific protocol type (paragraphs [0083], [0406).
Regarding claim 8, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 7, wherein the plurality of dynamic areas are operable to implement separate interfaces for communicating with respective field devices of a process control system (paragraph [0083]; Koch discloses that the communication bar may be invariant with respect to a reconfiguration of the dynamic part of the logic chip in that the basic structure of the communication bar is maintained in a reconfiguration of logic chip. On the other hand, the communication bar may be adapted by a reconfiguration of the logic chip in that a bypass connection segment existing between corresponding communication bar interface locations is replaced by an access structure inserted between the corresponding communication bar interface locations, or vice versa. Thus, the configuration (or reconfiguration) of the dynamic part of the logic circuit may result in a dynamic insertion of one or more access structures into a communication bar, or in a removal of one or more access structures from the communication bar).
Regarding claim 9, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 7, wherein the plurality of dynamic areas host fieldbus instances conforming to the same fieldbus protocol type (paragraphs [0021], [0031], [0213 – 0214]).
Regarding claim 10, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 7, wherein the plurality of dynamic areas host fieldbus instances conforming to different fieldbus protocol types (paragraphs [0021], [0031], [0213 – 0214]).
Regarding claim 11, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein the fieldbus stack hardware configuration that is used to program the at least one dynamic area is encrypted (paragraph [0333]; Koch discloses that the practical applications for partial runtime reconfiguration are manifold. For example, it may be used to exchange some modules after the start-up phase. In this case, an FPGA may be configured with test modules, boot-loader modules, or a cryptographic accelerator to speed up some authentication processes in a secure embedded system at start-up ).
Regarding claim 13, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 1, wherein the control circuitry comprises control logic programmed into the programmable logic and/or a processor system configured to run control software (paragraphs [0432], [0481], [0487]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Koch et al (US 2010/0283505; hereinafter Koch) in view of Kalogridis et al (US 2004/0073801; hereinafter Kalogridis).
Regarding claim 12, Koch discloses the dynamically reconfigurable fieldbus communications interface as claimed in claim 11, but fails to specifically disclose that the fieldbus stack hardware configuration is encrypted using asymmetric cryptography, wherein the programmable logic is configured to generate a public-private key pair, wherein the public key of the pair is usable to encrypt a partial bit-stream file for the at least one dynamic area, and wherein a private key of the pair is stored in memory.
Kalogridis, in an analogous art, discloses that the fieldbus stack hardware configuration is encrypted using asymmetric cryptography (paragraph [0020], [0024], [0035]; Kalogridis discloses that asymmetric cryptographic systems are generally used within an infrastructure known as Public Key Infrastructure (PKI) which provides key management functions. Asymmetric cryptography can also be used to digitally sign messages by encrypting either the message or a message digest, using the private key), wherein the programmable logic is configured to generate a public-private key pair, wherein the public key of the pair is usable to encrypt a partial bit-stream file for the at least one dynamic area, and wherein a private key of the pair is stored in memory (paragraphs [0068 – 0069]; Kalogridis discloses that in this variant of the protocol the secret key is kept secret from other entities not permitted to know the key, such as potentially malicious third parties. The secret key may comprise a key of a symmetric cryptographic algorithm, in which case the key is common to both the first and second entities and shared by the first entity with the second entity. Alternatively the secret key may comprise a private key, or preferably a public-private key pair of an asymmetric cryptographic algorithm).
Thus, it would have been obvious to one of ordinary skill the art before the effective filing date of the invention to modify the teaching of Koch by showing that the fieldbus stack hardware configuration is encrypted using asymmetric cryptography, wherein the programmable logic is configured to generate a public-private key pair, wherein the public key of the pair is usable to encrypt a partial bit-stream file for the at least one dynamic area, and wherein a private key of the pair is stored in memory as evidenced by Kalogridis for the purpose of providing improved performance and security in an efficient and reliable manner.
Claims 14 and 15 incorporate substantively all the limitations of claim 1 in method and computer-readable medium rather than device form. The reasons for rejecting claim 1 apply in claims 14 and 15. Therefore, claims 14 and 15 are rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fu et al (US 2019/0377907) discloses an integrated-chip-based data processing method, computing, device, and storage media.
Robert James al (US 2005/0228509) discloses system, device, and method for adaptively providing a fieldbus link.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YVES DALENCOURT whose telephone number is (571)272-3998. The examiner can normally be reached M-F 8AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ario Etienne can be reached at 571-272-4001. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YVES DALENCOURT/Primary Examiner, Art Unit 2457
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