DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on March 25, 2025 and April 7, 2025 have been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty (US 2021/0240641 A1, hereinafter Benisty) in view of Kim (US 2019/0171392 A1, hereinafter Kim).
Regarding claim 1, Benisty discloses a data storage device (figure 1, 102), comprising: a controller (figure 1, 110), wherein the controller comprises a controller memory buffer (CMB) (figure 1, 124 and [0030], storage device controller 110 also includes a memory controller 120, and storage memory 122 can further include a controller memory buffer (CMB) 124 for use by host 150) and wherein the controller is configured to: issue a write command to write data to a host memory buffer (HMB) of a host device ([0032], storage device controller 110 may also include a direct memory access (DMA) module 133 interacts with NVM 106 for read and write operations and executes data transfers between host 150 and storage device 102 without involvement from CPU 152) and issue a write command to the CMB to cache the write data in the CMB ([0064]-[0069], if the SGL descriptor is a SGL bit bucket descriptor. At block 760, the storage device controller transfers the data to a CMB 124 of the data storage device controller 110). Benisty differs from the claimed invention in not specifically disclosing that the controller is configured to determine whether a utilization of the CMB is greater than or equal to a threshold utilization; allocate a buffer of the CMB when the utilization of the CMB is less than the threshold utilization. However, Kim teaches a processor 212 may control an address mapping table regarding the CMB 216 to be updated by using a free buffer area in the CMB 216, in response to the write command including the WDS provided by the host 100 and may receive a threshold value of the free buffer area in the CMB 216 as a write buffer threshold from the host 100, and set the free buffer area in the CMB 126 as the write buffer threshold. The processor 212 may notify the host 100 that the free buffer area in the CMB 216 is below the write buffer threshold ([0039]-[0040]) in order to reduce a write completion latency. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Benisty in having that the controller is configured to determine whether a utilization of the CMB is greater than or equal to a threshold utilization; allocate a buffer of the CMB when the utilization of the CMB is less than the threshold utilization, as per teaching of Kim, in order to reduce a write completion latency.
Regarding claim 2, Benisty the write data is not programmed to the HMB ([0066], the storage device controller 110 activates the control path 142 to fetch the SGL descriptor associated with the requested data, and the SGL can be stored in host memory 160 or in a CMB 124 of the storage device controller 110).
Regarding claim 5, Benisty discloses that the data storage device does not include dynamic random access memory (DRAM) ([0021], a data storage device 102, such as a solid state drive (SSD)).
Regarding claim 8, Benisty discloses that the controller comprises a CMB-HMB scheduler ([0032], storage device controller 110 may also include a scheduler 134).
Regarding claim 9, Benisty teaches the CMB-HMB scheduler is configured to associate both the CMB and an HMB of a host device as a single buffer pool, wherein the single buffer pool comprises a plurality of CMB buffers and a plurality of HMB buffers ([0030-[0032], scheduler 134 controls the data transfer while activating the control path for fetching Scatter Gather Lists (SGLs), posting completion and interrupts, and activating the DMAs for the actual data transfer between host 150 and data storage device 102 and storage memory 122 can further include a controller memory buffer (CMB) 124 for use by host 150 such that the scheduler is configured to associate both CMB and HMB as a single buffer comprising a plurality of CMB buffers and a plurality of HMB buffers).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty (US 2021/0240641 A1, hereinafter Benisty) in view of Kim (US 2019/0171392 A1, hereinafter Kim) as applied in claim 1 above, and further in view of Shin et al. (US 2019/0065102 A1, hereinafter Shin).
Regarding claims 3-4, the combination of Benisty and Kim differs from the claimed invention in not specifically disclosing that the controller is further configured to: issue a read command to read the write data from the HMB; determine whether the write data is cached in the CMB; find a CMB address of the write data when the write data is cached in the CMB; and issue a read command to the CMB to read the write data from the CMB, wherein the write data is not read from the HMB. However, Shin teaches that the host may input read command to the memory system, memory controller of the memory system may first check whether first check whether data corresponding to the read command input from the host has been stored in the completion queue of the controller memory buffer in response to the read command such that the memory system may use the controller memory buffer as a first cache buffer, i.e., when the data corresponding to the read command is searched in the completion queue, the memory controller may immediately set the completion queue indicating that the processing of the read command has been completed, and the host may receive the data corresponding to the read command from the completion queue, thereby the write data is not read from the HMB, in order to improve read performance. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Benisty and Kim in having that the controller is further configured to: issue a read command to read the write data from the HMB; determine whether the write data is cached in the CMB; find a CMB address of the write data when the write data is cached in the CMB; and issue a read command to the CMB to read the write data from the CMB, wherein the write data is not read from the HMB, as per teaching of Shin, in order to improve read performance.
Allowable Subject Matter
Claims 6-7 and 10-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art Benisty (US 2021/0240641 A1) teaches storage device controller may include a scheduler and a controller memory buffer (CMB) or use by host ([0030]-[0032]). However, the prior art of record fails to teach nor suggest “wherein the controller further comprises aCMB/HMB scheduler, wherein the CMB/HMB scheduler is configured to dynamically allocate either a buffer of the CMB or a buffer of the HMB based on at least one of a latency of accessing either the CMB or the HMB and an availability of capacity of either the CMB or the HMB” as recited in claim 6; “wherein the CMB-HMB scheduler is configured to allocate either a CMB buffer from the plurality of CMB buffers or an HMB buffer from plurality of HMB buffers, wherein the allocating is based on a tradeoff between latency and performance between using the CMB or using the HMB to store data” as recited in claim 10; “wherein the CMB-HMB scheduler is further configured to: determine that an access request to write data to the HMB has been initiated; determine whether a utilization of the CMB is less than a utilization threshold; allocate the CMB buffer for the access request when the utilization of the CMB is less than the utilization threshold; and issue a CMB write command to write the data to the CMB instead of the HMB” as recited in claim 11; “wherein the CMB-HMB scheduler is further configured to: determine that an access request to read data from the HMB has been initiated; determine whether the data is cached in the CMB buffer; locate a CMB address of the CMB buffer associated with the data when the data is cached in the CMB buffer; and issue a CMB read command to read the data using the CMB address from the CMB instead of the HMB” as recited in claim 13; “wherein the CMB-HMB scheduler is further configured to: receive a write command to write data to the CMB from the host device; determine whether at least a portion of the CMB buffer has been allocated to cache data by the controller; and halt the write to the CMB when the at least the portion of the CMB buffer has been allocated to cache data by the controller” as recited in claim 15; and “wherein the CMB-HMB scheduler is further configured to move data stored in the CMB to the HMB or data stored in the HMB to the CMB based on an access frequency of the data stored in the CMB or the data stored in the HMB” as recited in claim 20.
Claims 7, 12, 14 and 16-19 are objected because of depending, either directly or indirectly, on claims 6, 11, 13 and 15, respectively, containing the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Benisty et al. (US 2024/0053923 A1) discloses a host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance (abstract and [0062]).
Navon et al. (US 2021/0286623 A1) discloses a storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array having an embedded FPGA being used to provide dynamic host memory buffer (HMB)—controller memory buffer (CMB) support for the controller, which can be useful in a Non-Volatile Memory Express (NVMe) environment (abstract and [0068]-[0075]).
Shin (US 2022/0269434) discloses utilization based dynamic shared buffer in data storage system, wherein allocating a buffer memory to a plurality of data storage zones (abstract, and figures 2 and 7).
Gissin et al. (US 2019/0272123) discloses method, device and system for controlling data read/write command in NVME over fabric architecture (abstract, figures 2, and 3A-3D).
Asano (US 11,372,753) discloses a memory system includes a NVM and a controller, the controller selects as a write mode with first and second modes with different bit data written per memory cell respectively (abstract, figure 11-13 and 17).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
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