DETAILED ACTION
Preliminary Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application is a continuation of PCT/KR2023/012728 filed 08/28/23 which further depends upon KR 10/2022-0135871 filed 10/20/22.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: #440-1, 440-2 of Figure 4 and #530 of Figure 5. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Publication 2017/0230603) and Venkitasubramani et al. (U.S. Publication 2020/0154120).
In reference to claim 1, Kim et al. discloses a display device (see paragraphs 9, 51 and Figure 2 wherein Kim et al. discloses a display apparatus and display method that allocates frame buffers based on a size and a location of a region of a screen.), comprising:
memory storing instructions (see paragraphs 100, 129, 140 and Figure 9); and
at least one processor operatively connected to the memory and comprising at least one graphic buffer and at least two scalers, wherein the at least one processor is configured to execute the instructions to (see paragraphs 39, 53, 68, 100, 126-129, 133, 140 and Figures 2, 3 and 9 wherein Kim et al. discloses the display apparatus comprising at least a processor that executes instructions stored in the storage device/memory of the display apparatus. Kim et al. further discloses the display apparatus comprising a graphic frame buffer further sectioned with a partial frame buffer. Kim et al. further discloses the display apparatus comprising a video processor that preforms scaling.):
obtain first graphic data from the memory (see paragraph 57 and #224, 230, 210 of Figure 2 wherein Kim et al. discloses obtaining at least one piece of graphic data to be displayed which is interpreted as inherently obtained from the at least graphic buffer.);
determine a size of the at least one graphic buffer to be upscaled by the at least two scalers, based on a resolution of the first graphic data and a resolution of the display device (see paragraphs 58-60, 62, 84-86, 102 and Figures 2, 6b and 8 wherein Kim et al. discloses the processor allocating at least one partial frame buffer based on a size and a location of a region on a screen of the display on which a user interface, comprising the obtained graphic data, is to be displayed. Kim et al. discloses utilizing the above mentioned partial frame buffer as allocation of the plurality of regions of display that are split into the region.);
render the first graphic data to the at least one graphic buffer to generate rendered data (see paragraph 55 and 130 wherein Kim et al. discloses that the user interface graphics are written/stored in at least the allocated partial frame buffer, the user interface eventually rendered to the display using a rendering module.);
divide the at least one graphic buffer into at least two division areas based on a specification of the at least two scalers;
upscale the rendered data of the at least two division areas using the at least two scalers to obtain at least two upscale graphic data;
obtain output graphic data by mixing the at least two upscale graphic data; and
control the display device to display the output graphic data.
Although Kim et al. does disclose rendering the graphic data to the display using a rendering module (see at least paragraph 130), Kim et al. does not explicitly disclose utilizing multiple scalers and dividing the memory/buffer based on the configuration/specification of the scalers. Venkitasubramani et al. discloses a video processor that slices an input image, scales the slices and then multiplexes the slices into a combined scaled output image (see paragraph 13). Venkitasubramani et al. discloses obtaining an input image and slicing the image into four slices, each slice representing a quartile of the input image (see paragraph 50 and #304, 308-1-4 of Figure 3). Venkitasubramani et al. further explicitly discloses each scaler processing a number of pixels in parallel (see paragraphs 26 and 46). Venkitasubramani et al. further explicitly discloses configuring a buffer so that each input slice provided to their own buffer (see at least paragraphs 63-64a and Figure 5). Venkitasubramani et al. then discloses passing each slice to their own respective scaler to perform upscaling on each of the slices (see paragraphs 51, 67 and #312-1-4 of Figure 3). Venkitasubramani et al. discloses a multiplexer which combines the four upscaled slices into a single output image (see paragraphs 52, 69 and Figures 3 & 5). Venkitasubramani et al. lastly discloses that once the output image is multiplexed and gathered, the image is driven to a display screen for display (see at least paragraph 92 and #724 of Figure 7). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement the parallel-slice upscaling techniques of Venkitasubramani et al. with the display apparatus buffering techniques of Kim et al. in order to meet the demands of rapidly increasing display resolutions requiring increased pixel throughput by distributing scaling workloads across multiple scaling units rather than trying to push clock speeds using singular scaling devices/apparatus (see at least paragraphs 20-22 of Venkitasubramani et al.).
In reference to claims 2 and 12, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 1 and 11 respectively. Kim et al. also discloses obtaining and processing multiple graphics data for the user interface (e.g. first, second “graphic data”) (see paragraphs 79, 81-82 and Figure 6A).
In reference to claims 3 and 13, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 2 and 12 respectively above. Kim et al. discloses each of the graphics data, #620a, 620b, rendered on a graphic plane corresponding to a size of a region on which the user interface is displayed which can be interpreted as “superimposed” or “overlaid” upon one another (see at least paragraphs 79, 81-82 and Figure 6A). Kim et al. further explicitly discloses each of the graphic planes stored in at least one partial frame buffer (see at least paragraph 79).
In reference to claims 4 and 14, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 1 and 11 respectively. Kim et al. discloses the display screen comprising a total number of pixels and further discloses the graphic frame buffer having a specific size for storing a resolution of pixels (see paragraph 85) thus the Examiner interprets the buffer at least inherently comprises a “ratio corresponding to the resolution of the display device.”
In reference to claims 5 and 15, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 4 and 14 respectively above. Although Kim et al. can at least inherently be interpreted as teaching the graphics data resolution as comprising a ratio as per the display screen resolution, neither Kim et al. nor Venkitasubramani et al. disclose such a ratio as specifically equal to 16:9, 21:9 or 32:9. At the time the invention was filed, it would have been obvious to one of ordinary skill in the art to implement the graphics buffer and scaling techniques of the combination of Kim et al. and Venkitasubramani et al. to implement a resolution of graphic data that satisfies the ratio of 16:9, 21:9 or 32:9. Applicant has not disclosed that explicitly configuring the graphic data ratio in such specific formats provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with techniques described in the combination of Kim et al. and Venkitasubramani et al. because the exact graphic memory/display ratio is seen as a matter of engineering design choice as preferred by the inventor and/or to which best suits the invention at hand. Therefore, it would have been obvious to one of ordinary skill in this art to modify the combination of Kim et al. and Venkitasubramani et al. to obtain the invention as specified in claims 5 and 15 respectively.
In reference to claims 6 and 16, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 5 and 15 respectively above. Venkitasubramani et al. discloses the input image frame sliced into four vertical slices (see paragraph 46 and Figure 2). As can be seen in at least Figure 2 of Venkitasubramani et al., slice 208-1 can be considered on an opposite or “second” side of the “vertical axis” or “vertical plane” as at least slice 208-4.
In reference to claims 7 and 17, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 6 and 16 respectively above. Although Venkitasubramani et al. does disclose the slices configured as each comprising the full vertical length of the display screen (see Figure 2) while being ¼ of the horizontal length (e.g. four slices), Venkitasubramani et al. does disclose an embodiment where the image frame is divided into N slices in which N = 2 to satisfy the limitations as indicated in claims 7 and 17 respectively. At the time the invention was filed, it would have been obvious to one of ordinary skill in the art to implement an N = 2-slice scaler in Venkitasubramani et al.. Applicant has not disclosed that explicitly configuring the slices to N = 2 or so that the horizontal length of each slice is half the display screen resolution, provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with teachings of the combination of Kim et al. and Venkitasubramani et al. because the exact number of slices used in the invention as described in the combination of Kim et al. and Venkitasubramani et al. is a matter of engineering design choice as preferred by the inventor and/or to which best suits the application at hand. Therefore, it would have been obvious to one of ordinary skill in this art to modify the combination of Kim et al. and Venkitasubramani et al. to obtain the invention as specified in claims 7 and 17 respectively.
In reference to claims 8 and 18, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 1 and 11 respectively. Kim et al. discloses the display apparatus comprising a display and an image input interface (see #115, 170, 171, 172, 173, 174 of Figure 9). Kim et al. further discloses the video processor performing a video decoding video frames that have been input and received via for example, an HDMI port (see paragraphs 68, 125 and #170, 110 of Figure 9). Kim et al. also discloses the display apparatus comprising a mixer that mixes both outputs of video and graphic data for display (see paragraphs 64-67).
In reference to claims 9, 10, 19 and 20, Kim et al. and Venkitasubramani et al. disclose all of the claim limitations as applied to claims 1 and 11 respectively. Venkitasubramani et al. discloses the slices configured as each comprising the full vertical length of the display screen (see Figure 2) while being ¼ of the horizontal length (e.g. four slices) while further disclosing the scaled slices are recombined to form a 4k image from a 1080p image (see paragraphs 46, 50-51 and Figure 2).
In reference to claim 11, claim 11 is similar in scope to claim 1 and is therefore rejected under like rationale. Claim 11 recites a “method” of the invention of which the Examiner believes has, at least inherently, been disclosed by the prior art techniques described in the rejection of claim 1 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Antonio Caschera whose telephone number is (571) 272-7781. The examiner can normally be reached Monday-Friday between 6:30 AM and 2:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Said Broome, can be reached at (571) 272-2931.
Any response to this action should be mailed to:
Mail Stop ____________
Commissioner for Patents
P.O. Box 1450
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or faxed to:
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See the listing of “Mail Stops” at http://www.uspto.gov/patents/mail.jsp and include the appropriate designation in the address above.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the Technology Center 2600 Customer Service Office whose telephone number is (571) 272-2600.
/Antonio A Caschera/
Primary Examiner, Art Unit 2612
9/14/26
Prosecution Insights