DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1).
Regarding claim 1:
Bibikar teaches:
An electronic device (Bibikar: computing device 100 [0010]) comprising:
display driver circuitry including
a graphic random access memory (GRAM) (Bibikar: The display controller 140 may include an internal memory buffer 142, for example a first-in-first-out (FIFO) buffer 142, that stores image data for display on the display 144. [0016]); and
a display panel (Bibikar: display 144 [0015]), wherein the display driver circuitry is configured to:
based on scanning an image in the GRAM having a first activation state obtaining power in a first range, display the image on the display panel (Bibikar: In block 304, the computing device 100 accesses the image data stored in the memory 132 using the display controller 140 and outputs the image data to the display 144. [0031]); and
in response to the scanning, change a state of the GRAM from the first activation state to a second activation state obtaining power in a second range for maintaining the image in the GRAM (Bibikar: the computing device 100 is configured to enter a low-power standby display refresh mode when displaying a static image on the display 144 [0010]),
wherein the power in the second range is lower than the power in the first range (see Note 1A), and
Note 1A: Bibikar teaches a “low-power” standby mode in [0010]. The Examiner submits that Bibikar’s teaching of entering a low-power mode suggests entering this mode from a high power active mode, such as the one described in [0023]: “The active display module 208 is configured to cause the display controller 140 to output an image to the display 144 in an active mode, such as an S0 mode.” One of ordinary skill in the art would understand that the lower power mode will obtain power in a second range that is lower than the power in a first range.
Bibikar fails to explicitly teach:
wherein a refresh rate for the image in the GRAM is lower than a reference refresh rate.
Goria teaches:
wherein a refresh rate for the image in the GRAM is lower than a reference refresh rate (Goria: a refresh rate of a display may be adjusted as a function of any desired aspect of the display of content, etc. In some embodiments, such refresh rate may be lowered for power saving purposes [0021]).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Goria with Bibikar. Having a refresh rate for the image lower than a reference refresh rate, as in Goria, would benefit the Bibikar teachings by reducing power draw: “Such feature may render power savings, since each refresh requires additional power by the display,” (Goria, [0016]).
Regarding claim 2:
Bibikar in view of Goria teaches:
The electronic device of claim 1 (as shown above), further comprising:
a processor comprising processing circuitry (Bibikar: The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory, Abstract), wherein the display driver circuitry is further configured to:
change the state of the GRAM from the second activation state to the first activation state (Bibikar: Wake events may be embodied as any external wakeup, timer-based wakeup, or other event causing the computing device 100 to return to the full-power, active state. [0035]), for receiving another image from the processor or scanning again the image (Bibikar: The active display module 208 is configured to cause the display controller 140 to output an image to the display 144 in an active mode [0023]).
Regarding claim 19:
Claim 19 is substantially similar to claim 1, and is therefore rejected for similar reasons. Claim 19 contains the following notable differences:
Claim 19 claims a method instead of a electronic device. In the rejection of claim 1, it was shown that Bibikar in view of Goria teaches the claimed electronic device. It follows that Bibikar in view of Goria teaches the corresponding method.
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Wyatt (US 20120207208 A1).
Regarding claim 3:
Bibikar in view of Goria teaches:
The electronic device of claim 2 (as shown above), wherein the display driver circuitry is further configured to:
based on receiving the another image from the processor, execute first displaying of the another image on the display panel and store the another image in the GRAM having the first activation state (Bibikar: The processor 120 and other components of the computing device 100 may generate the image data by rendering animated graphics, performing calculations, or otherwise operating in a fully operational, active mode, [0024]) changed from the second activation state (Bibikar: In block 346, the computing device 100 exits the display refresh standby mode. The computing device 100 may perform any routines required to exit the low-power display refresh standby mode and place the computing device 100 in an active, full-power mode such as the S0 active mode. [0037]); and
Bibikar in view of Goria fails to explicitly teach:
execute second displaying of the another image on the display panel at least by scanning the another image in the GRAM having the first activation state.
Wyatt teaches:
execute second displaying of the another image on the display panel at least by scanning the another image in the GRAM (Wyatt: While the display device 110 is in the panel self-refresh mode, SRC 220 continuously generates repeating video signals representing the cached pixel data stored in local frame buffers 224 for one or more consecutive video frames. [0038]) having the first activation state (see Note 3A).
Note 3A: Wyatt teaches that the same image may be displayed repeatedly within a low power mode (analogous to the claimed second activation state). However, Bibikar teaches that their active mode is “fully operational” [0024] and that “The active display module 208 may cause the display controller 140 to access image data from the memory 132” [0023], and therefore the Examiner submits that when the teachings of Wyatt are combined with Bibikar in view of Goria, it would be obvious to one of ordinary skill in the art that any functionality possible in the second activation state should be also possible in the first activation state, such as displaying a previous frame from memory.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria. Executing second displaying of the another image on the display panel at least by scanning the another image in the GRAM, as in Wyatt, would benefit the Bibikar in view of Goria teachings by allowing components unused by the system to be turned off while still displaying an image: “When in such a self-refresh mode, the video signals are driven by the local controller, thereby allowing portions of the graphics controller to be turned off to reduce the overall power consumption of the computer system.” [0004].
Regarding claim 18:
Bibikar in view of Goria teaches:
The electronic device of claim 1 (as shown above),
Bibikar in view of Goria fails to explicitly teach:
wherein the first activation state is provided based on a first voltage provided to the GRAM,
wherein the second activation state is provided based on a second voltage provided to the GRAM, and
wherein the second voltage is lower than the first voltage.
Wyatt teaches:
wherein the first activation state is provided based on a first voltage provided to the GRAM (see Note 18A),
wherein the second activation state is provided based on a second voltage provided to the GRAM (Wyatt: EC 310 transmits the GPU_PWR and FB_PWR signals to voltage regulators that provide a supply voltage to the GPU 240 and frame buffers 244, respectively. EC 310 also transmits the WARMBOOT, SELF_REF and RESET signals to GPU 240 [0063]; see Note 18A), and
wherein the second voltage is lower than the first voltage (Wyatt: When display device 110 enters the self-refresh mode, computer system 100 may also kill power to frame buffers 244 in order to further reduce overall power consumption of computer system 100. [0064]; see Note 18B).
Note 18A: Wyatt teaches that signals such as GPU_PWR and FB_PWR are transmitted by a voltage regulator, and that the modes of the system have corresponding signals (e.g., “The SELF_REF signal is asserted by EC 310 when display device 110 is operating in a panel self-refresh mode.” [0066]). The self-refresh mode is intended to cause lower power usage, as shown in [0064] cited above. Therefore, the Examiner submits that it would be obvious for the first and second activation states to be based on voltages provided to the GRAM and the second voltage to be lower than the first.
Note 18B: Wyatt teaches that power may be turned off to frame buffers based on entering the second activation state (the self-refresh mode).
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Lee (US 20210248980 A1).
Regarding claim 4:
Bibikar in view of Goria teaches:
The electronic device of claim 2 (as shown above), wherein the display driver circuitry is configured to:
display the image on the display panel the image in the GRAM (Bibikar: The active display module 208 may cause the display controller 140 to access image data from the memory 132, [0023]) having the first activation state (Bibikar: The active display module 208 is configured to cause the display controller 140 to output an image to the display 144 in an active mode, such as an S0 mode [0023]) changed from the second activation state (Bibikar: The computing device 100 may perform any routines required to exit the low-power display refresh standby mode and place the computing device 100 in an active, full-power mode such as the S0 active mode. [0037]).
Bibikar in view of Goria fails to explicitly teach:
display the image on the display panel at least by scanning again the image in the GRAM having the first activation state changed from the second activation state.
Lee teaches:
display the image on the display panel at least by scanning again the image in the GRAM (Lee: A display device driven using commands may read data (e.g., an image frame) from a memory (e.g., graphic random-access memory (GRAM)) and output the image via a display panel in […] In this case, the display driver IC may read data (e.g., image frames) and transmit the data to the display (e.g., panel) during a scan-on time [0004], (emphasis added)).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Lee with Bibikar in view of Goria. Displaying the image on the display panel at least by scanning again the image in the GRAM, as in Lee, would benefit the Bibikar in view of Goria teachings by enabling the reading of GRAM to be properly timed such that battery life can be saved: “[Data is transmitted] during a scan-on time for every period (e.g., every interval) of the synchronization signal (e.g., VSYNC signal).” [0004]; “The interval of the synchronization signal (e.g., VSYNC signal) described above may correspond to the refresh rate of the display. The processor may dynamically change the interval of the synchronization signal (e.g., VSYNC signal) to dynamically change the refresh rate of the display depending on whether a high responsiveness is required or whether longer battery life is needed (e.g., whether low power consumption is needed).” [0006]
Regarding claim 20:
Claim 20 is substantially similar to claim 4, and is therefore rejected for similar reasons. Claim 20 contains the following notable differences:
Claim 20 claims a method instead of a electronic device. In the rejection of claim 1, it was shown that Bibikar in view of Goria and Lee teaches the claimed electronic device. It follows that Bibikar in view of Goria and Lee teaches the corresponding method.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Kwa (US 20140111531 A1).
Regarding claim 5:
Bibikar in view of Goria teaches:
The electronic device of claim 2 (as shown above), wherein the display driver circuitry is configured to:
obtain, from the processor, a control command indicating to activate the GRAM for displaying on the display panel (Bibikar: Wake events may be embodied as any external wakeup, timer-based wakeup, or other event causing the computing device 100 to return to the full-power, active state. […] the computing device 100 may power up components required to access the display buffer 134, [0035]; Bibikar: the display controller 140 outputs an image from its internal FIFO buffer 142 to the display 144 for display [0034]);
Bibikar in view of Goria fails to explicitly teach:
in response to the control command, change the state of the GRAM from a deactivation state to the first activation state;
based on receiving, from the processor, the image after the state of the GRAM is changed from the deactivation state to the first activation state, execute first displaying of the image on the display panel and store the image in the GRAM having the first activation state changed from the deactivation state; and
display the image on the display panel at least by executing second displaying of the image in accordance with scanning the image in the GRAM having the first activation state.
Kwa teaches:
in response to the control command, change the state of the GRAM from a deactivation state (see Note 5A) to the first activation state (Kwa: In response to signal SRD_ON from a host, SRD control block activates the frame buffer [0018]);
based on receiving, from the processor, the image after the state of the GRAM is changed from the deactivation state to the first activation state, execute first displaying of the image on the display panel (Kwa: and the SRD control block controls the multiplexer (MUX) to transfer the captured frame to the output port [0018]) and store the image in the GRAM having the first activation state changed from the deactivation state (Kwa: In response to signal SRD_ON from a host, SRD control block activates the frame buffer to capture a frame [0018]); and
display the image on the display panel at least by executing second displaying of the image in accordance with scanning the image in the GRAM having the first activation state (Kwa: Timing controller 180 has the capability to respond to instructions from a host device to enter a self refresh mode that may include […] capturing an image and repeatedly outputting the captured image to a display. [0018]; (emphasis added)).
Note 5A: Kwa teaches: “After the signal SRD_ON is deactivated, SRD control block deactivates the frame buffer” [0018]. That is, prior to the SRD_ON signal from a host, the frame buffer is deactivated.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Kwa with Bibikar in view of Goria. Changing the state of the GRAM from a deactivation state to the first activation state, as in Kwa, would benefit the Bibikar in view of Goria teachings by maximizing power savings by powering down components to the lowest level: “powering down components may involve reducing voltage regulators to the lowest operating voltage level” [0014].
Claims 6, 7, 9, 10, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1), Kwa (US 20140111531 A1) and Wyatt (US 20120207208 A1).
Regarding claim 6:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the display driver circuitry is configured to:
Bibikar in view of Goria and Kwa fails to teach:
obtain, from the processor, the control command in a first time interval being before a second time interval;
in a portion of the second time interval, execute the reception of the image from the processor, the first displaying of the image, the storing of the image, and the second displaying of the image in accordance with the scanning of the image; and
in another portion of the second time interval, change the state of the GRAM from the first activation state to the second activation state, and
wherein the state of the GRAM is to be changed to the first activation state before a third time interval being after the second time interval.
Wyatt teaches:
obtain, from the processor, the control command in a first time interval being before a second time interval (Wyatt: In the normal state 410, display device receives video signals from GPU 240. TCON 210 drives the LCD device 216 using the video signals received from GPU 240. In the normal operating state, display device 110 monitors communications path 280 to determine if GPU 240 has issued a panel self-refresh entry request. If display device 110 receives the panel self-refresh entry request, then display device 110 transitions to a wake-up frame buffer state 420. [0068]; see Note 6B);
in a portion of the second time interval, execute the reception of the image from the processor (Wyatt: In the cache frame state 430, display device 110 waits for the next falling edge of the VSync signal generated by GPU 240 to begin caching one or more frames of video in local frame buffers 224 [0070]), the first displaying of the image, the storing of the image, and the second displaying of the image in accordance with the scanning of the image (Wyatt: In one embodiment, GPU 240 may indicate how many consecutive frames of video to store in local frame buffers 224 by writing a value to a control register in display device 110. [0070]); and
in another portion of the second time interval, change the state of the GRAM from the first activation state to the second activation state (Wyatt: After display device has stored the one or more frames of video in local frame buffers 224, display device 110 transitions to a self-refresh state 440. [0070]), and
wherein the state of the GRAM is to be changed to the first activation state (Wyatt: In the wake-up frame buffer state 420, display device 110 wakes-up the local frame buffers 224 [0069]) before a third time interval being after the second time interval (Wyatt: In one embodiment, display device 110 may be required to initialize the local frame buffers 224 before the next frame of video is received over communications path 280 (i.e., before the next rising edge of the VSync signal generated by GPU 240). [0069]).
Note 6A: The Examiner interpreted the intervals to map to the teachings of Wyatt as follows:
First interval ends before the falling-edge of the VSync signal.
Second interval starts at the falling-edge of the VSync signal and ends before the rising-edge of the VSync signal.
Third interval starts after the rising-edge of the VSync signal.
Note 6B: The Examiner notes that the latter three limitations of claim 6 describe operations that all happen during the second time interval, but before the third time interval. Therefore, when Wyatt teaches receiving requests to change from the normal state 410 to the frame-buffer state 420, the Examiner interpreted that period to be the first time interval.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria and Kwa. Processing video commands based on the VSync intervals, as in Wyatt, would benefit the Bibikar in view of Goria and Kwa teachings by preventing screen tearing (i.e., displaying of an incomplete frame on the display) by waiting until the next vertical blanking period: “GPU 240 delays generating video signals until the display device 110 finishes driving LCD device 216 for the current frame of pixel data. After the video signals generated by SRC 220 reach the next vertical blanking period, display device 110 transitions to driving the LCD device 216 with the digital video signals generated by GPU 240.” (Wyatt, [0098]).
Regarding claim 7:
Bibikar in view of Goria, Kwa, and Wyatt teaches:
The electronic device of claim 6 (as shown above), wherein a start timing of each of the first time interval, the second time interval, and the third time interval corresponds to a timing for executing an image transmission from the processor to the display driver circuitry (see Note 7A).
Note 7A: In Note 6A, the Examiner discussed the interpretation of the periods as mapped to time intervals in Wyatt. All three intervals are related to the timing of the VSync signal that is “associated with the video signals generated by GPU 240” [0097]. Therefore, the Examiner interprets all three intervals to correspond to a timing for executing an image transmission from the processor to the display driver circuitry.
Regarding claim 9:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above),
Wyatt teaches:
wherein providing power to the GRAM is ceased in the deactivation state (Wyatt: In the GPU power-off state 550, EC 310 shuts down GPU 240 by turning off the voltage regulator supplying power to GPU 240. EC 310 may drive the GPU_PWR signal low to shut down the voltage regulator supplying GPU 240. [0079]).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria and Kwa. Not providing power to the GRAM in the deactivation state, as in Wyatt, would benefit the Bibikar in view of Goria and Kwa teachings by further reducing power usage.
Regarding claim 10:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the processor is configured to:
Bibikar in view of Goria and Kwa fails to explicitly teach:
based on the refresh rate for the image being lower than the reference refresh rate, provide the control command to the display driver circuitry
Wyatt teaches:
based on the refresh rate for the image being lower than the reference refresh rate, provide the control command to the display driver circuitry (Wyatt: If the number of consecutive frames of static video is greater than or equal to a first threshold value, then GPU 240 proceeds to step 814 where GPU 240 enters a deep-idle state 520. [0087]; see Note 10A).
Wyatt teaches: “In the deep-idle state 520, GPU 240 still generates video signals for display on display device 110 […] Additionally, GPU 240 may send a message to display device 110 requesting display device 110 to drive LCD device 216 at a lower refresh rate. For example, GPU 240 may request display device 110 to reduce the refresh rate from 75 Hz to 30 Hz, and GPU 240 may generate and transmit video signals based on the lower refresh rate.” [0075] (emphasis added). In other words, Wyatt teaches that the GPU may enter a deep-idle state based on the refresh rate of an video being lower (i.e., a number of static frames is higher than) a reference value. The GPU can then provide signals or commands based on the that lowered refresh rate.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria and Kwa. Providing commands based on a lower refresh rate, as in Wyatt, would benefit the Bibikar in view of Goria and Kwa teachings by saving power by reducing the rate at which frames should be displayed by the GPU: “GPU 240 operates in a power saving mode, such as by clock-gating or power-gating certain processing portions of GPU 240 while keeping the portions of GPU 240 responsible for generating the video signals active” [0075].
Regarding claim 11:
Bibikar in view of Goria, and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the display driver circuitry is further configured to:
Bibikar in view of Goria, and Kwa fails to teach:
receive, from the processor, another image subsequent to the image; and
based on the another image and/or a timing capable of receiving the another image, bypass storing in the GRAM the another image at least by changing the state of the GRAM to the deactivation state in accordance with the control command and display on the display panel the another image.
Wyatt teaches:
receive, from the processor, another image subsequent to the image (Wyatt: GPU 240 may count a consecutive number of frames that remain static and compare the number to one or more threshold values to detect one or more levels of idleness [0074]); and
based on the another image and/or a timing capable of receiving the another image (Wyatt: If the number of frames of video is greater than or equal to a third threshold value, then GPU 240 proceeds to step 830 where GPU 240 transitions to a GPU power-off state 550 [0091]; see Note 11A), bypass storing in the GRAM the another image at least by changing the state of the GRAM to the deactivation state (Wyatt: if GPU 240 detects a third level of idleness in the pixel data, then GPU 240 transitions to a GPU power-off state 550. [0078]) in accordance with the control command and display on the display panel the another image (Wyatt: The display device caches one or more static frames of video in the local frame buffer for use by the self-refresh controller for generating the video signals used to drive the display device while in self-refresh mode [0114]).
Note 11A: Each frame generated by the system will inherently take a given amount of time to generate. Wyatt describes that the GPU will count the number of frames, and based on the amount of frames, the GPU may turn off power. The Examiner submits that a counting a threshold amount of static (unchanging) frames is analogous to determining a threshold amount of time where the frame has not changed.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria and Kwa. Bypassing storing in the GRAM the another image at least by changing the state of the GRAM to the deactivation state, as in Wyatt, would benefit the Bibikar in view of Goria and Kwa teachings by further reducing power usage: “if GPU 240 detects a third level of idleness in the pixel data, then GPU 240 transitions to a GPU power-off state 550” (Wyatt, [0078])
Regarding claim 12:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the display driver circuitry is further configured to:
Bibikar in view of Goria and Kwa fails to teach:
based on the control command, change the state of the GRAM from the second activation state to the first activation state before a timing capable of starting an image transmission from the processor to the display driver circuitry;
store another image, subsequent to the image, received from the processor based on the timing, in the GRAM having the first activation state, and display, on the display panel, the another image; and
display again, on the display panel, the another image in accordance with scanning the other image in the GRAM having the first activation state.
Wyatt teaches:
based on the control command, change the state of the GRAM from the second activation state to the first activation state (Wyatt: In the wake-up frame buffer state 420, display device 110 wakes-up the local frame buffers 224 [0069]) before a timing capable of starting an image transmission from the processor to the display driver circuitry (Wyatt: display device 110 may be required to initialize the local frame buffers 224 before the next frame of video is received over communications path 280 (i.e., before the next rising edge of the VSync signal generated by GPU 240) [0069]);
store another image, subsequent to the image, received from the processor based on the timing, in the GRAM having the first activation state (Wyatt: In the cache frame state 430, display device 110 waits for the next falling edge of the VSync signal generated by GPU 240 to begin caching one or more frames of video in local frame buffers 224 [0070]; Wyatt: After display device has stored the one or more frames of video in local frame buffers 224, display device 110 transitions to a self-refresh state 440. [0070]), and display, on the display panel, the another image (Wyatt: In the self-refresh state 440, the display device 110 enters a panel self-refresh mode where TCON 210 drives the LCD device 216 with video signals generated by SRC 220 based on pixel data stored in local frame buffers 224 [0071]); and
display again, on the display panel, the another image in accordance with scanning the other image in the GRAM having the first activation state (see Note 12A).
Note 12A: Wyatt teaches “caching one or more frames of video in local frame buffers 224” [0070] and then “drives the LCD device 216 with video signals generated by SRC 220 based on pixel data stored in local frame buffers 224”. In the event that one frame of video is stored within the local frame buffer, the display panel would display only the one frame during the first activation state. Therefore, the Examiner understands Wyatt to teach “display[ing] again, on the display panel, the another image in accordance with scanning the other image in the GRAM having the first activation state”.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wyatt with Bibikar in view of Goria and Kwa. Displaying again, on the display panel, the another image in accordance with scanning the other image in the GRAM having the first activation state, as in Wyatt, would benefit the Bibikar in view of Goria and Kwa teachings by using less memory for local buffers while preserving low power usage: “The panel may resume rendering images from main memory when the displayed image changes. The amount of local memory required by DSR-capable panels tends to increase with increasing display resolution. Thus, larger or higher-resolution displays may require larger amounts of local memory and thus may be increasingly expensive.” (Bibikar, [0001])
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Kwa (US 20140111531 A1), Munteanu (US 8466864 B2; see attachment for paragraph numbers) and Wikipedia (NPL: Pulse-width modulation).
Regarding claim 8:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the display driver circuitry is configured to:
Bibikar in view of Goria and Kwa fails to teach:
based on a width of a pulse signal periodically transmitted from the processor to the display driver circuitry, obtain the control command.
Munteanu teaches:
based on a width of a pulse signal periodically transmitted from the processor to the display driver circuitry, obtain the control command (Munteanu: The backlight control signal 126 can enable or disable the backlight 110 by, for example, enabling or disabling a voltage input to the backlight 110, by directing a pulse width modulation (PWM) controller to provide a particular duty cycle signal to the backlight 110 (16); see Note 8A).
Note 8A: Munteanu teaches utilization of a pulse width modulation to signal to a backlight whether to turn on or off. Notably, Munteanu does so to “enable the backlight 110 during the normal mode and to disable the backlight 110 during the low-power mode, thereby further reducing power consumption during the low-power mode”. Because the other cited prior art, such Bibikar, also are directed to reducing power consumption by sending a signal to activate and deactivate a self-refresh mode that turns off components when the screen is static, the Examiner submits that it would be obvious to send a signal for the control command based on the width of a pulse signal.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Munteanu with Bibikar in view of Goria and Kwa. Obtaining the control command based on a pulse width, as in Munteanu, would benefit the Bibikar in view of Goria and Kwa teachings because utilizing pulse width modulation to transfer commands is known to be efficient in the art: “The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there is practically no current, and when it is on and power is being transferred to the load, there is almost no voltage drop across the switch. Power loss, being the product of voltage and current, is thus in both cases close to zero.” (Wikipedia, NPL: Pulse-width modulation, Pg. 1, par. 2)
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) Kwa (US 20140111531 A1) and Holland (US 20150287351 A1).
Regarding claim 13:
Bibikar in view of Goria and Kwa teaches:
The electronic device of claim 5 (as shown above), wherein the display driver circuitry is configured to:
Bibikar in view of Goria and Kwa, fails to teach:
change the state of the GRAM from the deactivation state to the first activation state to have a reference time interval between a first time interval in which the GRAM has the deactivation state and a second time interval in which the GRAM has the first activation state.
Holland teaches:
change the state of the GRAM (Holland: memory 12 may be implemented in static RAM (SRAM), or any RAM in the dynamic RAM (DRAM) family [0023]) from the deactivation state to the first activation state to have a reference time interval between a first time interval in which the GRAM has the deactivation state and a second time interval in which the GRAM has the first activation state (Holland: As the vertical blanking interval is coming to an end, the video timing and control unit 42 may generate another indication that the display will become active within some predetermined and programmable amount of time [0031]; see Note 13A and Note 13B)
Note 13A: Holland teaches: “This indication may serve as a wakeup to those components that were inactive” [0031] and that “The memory controller 22 may generally include circuitry for receiving memory operations from the other components of the processing system 10 and for accessing the memory 12” [0023]. Therefore, when combined with Bibikar in view of Goria and Kwa, the Examiner submits that it would be obvious to wake up the GRAM component based on a programmable amount of time as described in Holland.
Note 13B: In this instance, the Examiner interpreted the claimed first time interval to be analogous to the end of the blanking interval in Holland, and the claimed second time interval to be analogous to the time when the display becomes active in Holland.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Holland with Bibikar in view of Goria and Kwa. Introducing a reference period during the vertical blanking interval, as in Holland, would benefit the Bibikar in view of Goria and Kwa teachings by enabling use of the vertical blanking period to modify the power states of components, since said components may not be able to quickly change states: “because data is not displayed during the VBI, some display components take advantage of this time period and may go to an inactive state to save power. However, in many conventional low power systems, additional power reductions may be forfeited due to lack of coordination between display components and other system components” (Holland, [0005]).
Regarding claim 14:
Bibikar in view of Goria, Kwa, and Holland teaches:
The electronic device of claim 13 (as shown above), wherein the reference time interval is scheduled between the first time interval and the second time interval, for providing, to the GRAM, the power in the first range (Holland: In response to receiving or otherwise detecting the deasserted display inactive indication (block 345), the PMU 18 may transition a component from an inactive, power down or low power state to an active state (block 350) by powering up or re-starting gated clocks of the component. [0036]).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Holland (US 20150287351 A1).
Regarding claim 15:
Bibikar in view of Goria teaches:
The electronic device of claim 2 (as shown above), wherein the display driver circuitry is configured to:
Bibikar in view of Goria fails to teach:
change the state of the GRAM from the first activation state to the second activation state so as to have a reference time interval between at least a first time interval in which the GRAM has the first activation state and a second time interval in which the GRAM has the second activation state; and
change the state of the GRAM from the second activation state to the first activation state to have the reference time interval between at least the second time interval and the first time interval.
Holland teaches:
change the state of the GRAM from the first activation state to the second activation state so as to have a reference time interval (Holland: the video timing and control unit 42 may generate and provide a display inactive indication that indicates that the display will be entering the vertical blanking interval within a predetermined amount of time that may correspond to a predetermined number of lines. [0029]) between at least a first time interval in which the GRAM has the first activation state and a second time interval in which the GRAM has the second activation state (Holland: the vertical blanking interval may begin for the display 20, during which time, no data frames are displayed and no pixel data is fetched from memory. As such, in one embodiment, one or more portions of the display processing unit 16 may be placed into a low power state […] Components that receive the indication may use it to […] enter an inactive or low power state while the display is inactive and the display processing unit is not fetching pixel data from memory [0029]; see Note 15A and Note 15B); and
change the state of the GRAM from the second activation state to the first activation state to have the reference time interval between at least the second time interval and the first time interval (Holland: As the vertical blanking interval is coming to an end, the video timing and control unit 42 may generate another indication that the display will become active within some predetermined and programmable amount of time. This indication may serve as a wakeup to those components that were inactive. [0031]; see Note 15A and Note 15B).
Note 15A: Holland teaches: “Components that receive the indication [that indicates that the display will be entering the vertical blanking interval within a predetermined amount of time] may use it to […] enter an inactive or low power state while the display is inactive and the display processing unit is not fetching pixel data from memory” [0031] and that “[The indication that the vertical blanking interval is coming to an end] may serve as a wakeup to those components that were inactive” [0031]. Therefore, when combined with Bibikar in view of Goria and Kwa, the Examiner submits that it would be obvious to set the GRAM component to use the first or second activation state based on a programmable amount of time as described in Holland.
Note 15B: In this instance, the Examiner interpreted the claimed first time interval to be analogous to the start of the blanking interval in Holland, and the claimed second time interval to be analogous to the end of the blanking interval in Holland.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Holland with Bibikar in view of Goria and Kwa. Introducing a reference period during the vertical blanking interval, as in Holland, would benefit the Bibikar in view of Goria and Kwa teachings by enabling use of the vertical blanking period to modify the power states of components, since said components may not be able to quickly change states: “because data is not displayed during the VBI, some display components take advantage of this time period and may go to an inactive state to save power. However, in many conventional low power systems, additional power reductions may be forfeited due to lack of coordination between display components and other system components” (Holland, [0005]).
Regarding claim 16:
Bibikar in view of Goria and Holland teaches:
The electronic device of claim 15 (as shown above), wherein the reference time interval is scheduled between the first time interval and the second time interval to
change the power in the first range to the power in the second range (Holland: The display processing unit may include a timing control unit that may generate an indication that indicates that a display unit will enter an inactive state, such as for example, during a vertical blanking interval. In response to receiving the indication one or more of the video processing components may enter a low power state. In this way, it may be possible to improve power consumption, [0006]) or
change the power in the second range to the power in the first range (Holland: In response to receiving or otherwise detecting the deasserted display inactive indication (block 345), the PMU 18 may transition a component from an inactive, power down or low power state to an active state (block 350) by powering up or re-starting gated clocks of the component [0036]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Bibikar (US 20160267883 A1) in view of Goria (US 20080143728 A1) and Nakamura (US 20180293949 A1).
Regarding claim 17:
Bibikar in view of Goria teaches:
The electronic device of claim 2 (as shown above), wherein the display driver circuitry is further configured to:
Bibikar in view of Goria fails to teach:
after the image is displayed on the display panel,
obtain, from the processor, a control command indicating to cease activating the GRAM;
based on the control command, identify a time length in which displaying of the image on the display panel is maintained;
in response to the time length being longer than a reference length, change the state of the GRAM from the second activation state to the first activation state to store another image received from the processor after the control command is obtained and scan the another image stored in the GRAM; and
in response to the time length being shorter than the reference length, change the state of the GRAM from the second activation state to the deactivation state to bypass storing the other image in the GRAM in accordance with the control command.
Nakamura teaches:
after the image is displayed on the display panel (Nakamura: Thereafter, LCD driving information is obtained as driver status information from the display device 11 (Step S56) by using commands based on MIPI-DSI Standards. [0154]; see Note 17B),
obtain, from the processor, a control command indicating to cease activating the GRAM (Nakamura: the interface section 31 is configured to stop or start specific circuits within the display control circuit 200 upon issuance of a predetermined command from the host, and turn off power supply to said specific circuits [0115]);
based on the control command, identify a time length in which displaying of the image on the display panel is maintained (Nakamura: assume an intermission state for an intermission period determined as the non-refreshing period at most upon detection of a non-update of the image data in the image buffer for a predetermined period by the update detection section; [0011]);
in response to the time length being longer than a reference length (Nakamura: display image must be refreshed for every predetermined period which is longer than one frame period [0003]), change the state of the GRAM from the second activation state to the first activation state to store another image received from the processor after the control command is obtained (Nakamura: when the refreshing start timer times out, video signal output by the DSI section 106 is resumed; the host and the LCD return to Normal State; [0204]) and scan the another image stored in the GRAM (Nakamura: and in order to refresh the display image in the LCD, refreshing frame data (data representing the display image C) is sent from the host to the LCD (Steps S35 and S34; (4) in FIG. 16). [0204]); and
in response to the time length being shorter than the reference length, change the state of the GRAM from the second activation state (Nakamura: stops a first circuit defined as a circuit which has time required for resuming operation not longer than a predetermined time among circuits to be stopped in the display device in the intermission state [0028]) to the deactivation state to bypass storing the other image in the GRAM in accordance with the control command (Nakamura: without extending the memory area of the image buffer, if the intermission period is not longer than the predetermined reference period [0028]; see Note 17A).
Note 17A: The Examiner interprets “extending the memory area of the image buffer” as used in the Nakamura reference to be analogous to a storage operation relating to an extension of how long the existing image is to be displayed. Nakamura teaches: “When a host shifts to Intermission State 2 together with an LCD without data updating in an image buffer in the host, the image buffer is extended (extended from 2 frames (A, B) to 4 frames (A-D)).” (Abstract). As best understood by the Examiner, in the example cited in [0028] above, when the intermission period is shorter than the reference period, Nakamura bypasses both updating the image buffer as well as updating the time the image buffer is displayed.
Note 17B: Nakamura teaches that commands may be issued at step S56 (see Fig. 10) as cited above. Fig. 9 of Nakamura is the other portion of the loop shown in Fig. 10 which contains step S35: “Step S35 causes the DSI section 106 to resume its operation for transferring display image data to the display device 11”. Because the operations S35 and S56 are part of a loop, the Examiner submits that it would be obvious to perform the steps of claim 17 as described in Nakamura after the image is displayed on the display panel.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Nakamura with Bibikar in view of Goria. Determining the activation state of GRAM based on a time length being longer or shorter than a reference length, as in Nakamura, would benefit the Bibikar in view of Goria teachings by ensuring that the static image is still present in memory even during long self-refresh cycles: “when the number of intermission portions increases, the time required for the display device to return from the intermission state to the normal state becomes long. Therefore, when the number of intermission portions is increased, in the main body frame buffer configuration as described above, there may be a case where the image data for refreshing the display image is missing.” [0006].
Conclusion
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/VINCENT ALEXANDER PROVIDENCE/Examiner, Art Unit 2617 /KING Y POON/Supervisory Patent Examiner, Art Unit 2617
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