CTNF 19/090,283 CTNF 89467 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-23 are pending. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1, 2, 5, 9-11, 14-16, 19, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over UM (US 2022/0171569) (hereinafter UM) (published June 02, 2022) and Hwang (US 2015/0193157) (hereinafter Hwang) (published July 09, 2015) . Regarding Claims 1 and 15 , taking claim 15 as exemplary, UM discloses a memory system, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system to: “When implemented in at least partially in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, managers, interfaces, decoders, drivers, generators and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device ” (UM [0165]) receive first data from a first external system for storage, wherein the memory system supports a plurality of external systems that includes the first external system; “Further, the first and second memory interfaces 150 and 160 may transmit write data to the nonvolatile memory device 200 or receive read data from the nonvolatile memory device 200 ” (UM [0101] see Fig. 2, first external system is 210 ) “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103]) “ The memory may be configured to include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device 200 from the host device 20 or read data from the nonvolatile memory device 200 and to be transmitted to the host device 20. For example, the memory may operate as a buffer memory . The memory may be provided inside or outside the controller 100” (UM [0104]) executing, based on first metadata stored in a first storage region of the memory system, a first set of flash translation layer functions associated with management of the first memory region, the first metadata comprising first instructions associated with the first set of flash translation layer functions; “The first FTL core 120 may be configured of a micro control unit (MCU) and a central processing unit (CPU). The first FTL core 120 may process requests transmitted from the host device 20. To process the requests transmitted from the host device 20, the first FTL core 120 may drive a code-type instruction or algorithm (for example, firmware) loaded into a memory (not shown) and control operations of internal elements such as the protocol core 110, the common memory 140, and the first memory interface 150, and the nonvolatile memory device 200 ” (UM [0056]) “The memory may store firmware driven through the first and second FTL cores 120 and 130 . The memory may store data required for driving of the firmware, for example, metadata . For example, the memory may operate as a working memory of the first and second FTL cores 120 and 130” (UM [0103]) receive second data from a second external system for storage, wherein the plurality of external systems includes the second external system; and “Further, the first and second memory interfaces 150 and 160 may transmit write data to the nonvolatile memory device 200 or receive read data from the nonvolatile memory device 200 ” (UM [0101] see Fig. 2, second external system is 220 ) “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103]) “ The memory may be configured to include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device 200 from the host device 20 or read data from the nonvolatile memory device 200 and to be transmitted to the host device 20. For example, the memory may operate as a buffer memory . The memory may be provided inside or outside the controller 100” (UM [0104]) executing, based on second metadata stored in a second storage region of the memory system, a second set of flash translation layer functions associated with management of the second memory region, the second metadata comprising second instructions associated with the second set of flash translation layer functions. “The first FTL core 120 may be configured of a micro control unit (MCU) and a central processing unit (CPU). The first FTL core 120 may process requests transmitted from the host device 20. To process the requests transmitted from the host device 20, the first FTL core 120 may drive a code-type instruction or algorithm (for example, firmware) loaded into a memory (not shown) and control operations of internal elements such as the protocol core 110, the common memory 140, and the first memory interface 150, and the nonvolatile memory device 200 ” (UM [0056]) “ The above-described operation of the first FTL core 120 may also be applied to the second FTL core 130 ” (UM [0058]) “The memory may store firmware driven through the first and second FTL cores 120 and 130 . The memory may store data required for driving of the firmware, for example, metadata . For example, the memory may operate as a working memory of the first and second FTL cores 120 and 130” (UM [0103]) But does not explicitly state first data from a first external system for storage in a first memory region of the memory system and second data from a second external system for storage in a second memory region of the memory system . Hwang discloses first data from a first external system for storage in a first memory region of the memory system and second data from a second external system for storage in a second memory region of the memory system . “Referring to FIG. 4, the NAND flash memory device 100 may include first through third page buffers 120-1, 120-2, and 120-3, and the memory controller 200 may include first through third buffer memories 220-1, 220-2, and 220-3 ” (Hwang [0050] see Fig. 4, the buffer memories in the memory controller are associated with the respective set of memories in the NAND flash ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the buffers corresponding to individual flash memories of Hwang with the system in UM. The motivation for doing so would be to improve access latency associated with accessing flash memory for data. Regarding Claims 2 and 16 , UM further discloses wherein receiving the first data and the second data comprises: receiving the first data via a first port, wherein the memory system comprises a plurality of ports that includes the first port, and wherein the first port is operable to couple the memory system with the first external system, the first port associated with the first memory region; and receiving the second data via a second port of the plurality of ports of the memory system, wherein the second port is operable to couple the memory system with the second external system, the second port associated with the second memory region. “Further, the first and second memory interfaces 150 and 160 may transmit write data to the nonvolatile memory device 200 or receive read data from the nonvolatile memory device 200 ” (UM [0101] see Fig. 2, the two ports are coupled to external system 210 and 220 ) Regarding Claims 10 , UM discloses a memory system, comprising: a memory device, “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103]) wherein the memory system supports a plurality of external systems that includes the first external system and the second external system; and “Further, the first and second memory interfaces 150 and 160 may transmit write data to the nonvolatile memory device 200 or receive read data from the nonvolatile memory device 200 ” (UM [0101] see Fig. 2, the first external system is 210 and second external system is 220 ) one or more controllers coupled with the memory device, the one or more controllers operable to execute one or more flash translation layer functions to manage data for the plurality of external systems supported by the memory system, wherein: “In an embodiment, the controller 100 may include a protocol core 110, the first FTL core 120, the second FTL core 130 , a common memory 140, the first memory interface 150, and the second memory interface 160” (UM [0052]) the memory device is operable to store first metadata to support a first set of flash translation layer functions, wherein the first set of flash translation layer functions is associated with management of first data stored in the first memory region; and “ The memory may store firmware driven through the first and second FTL cores 120 and 130. The memory may store data required for driving of the firmware, for example, metadata . For example, the memory may operate as a working memory of the first and second FTL cores 120 and 130” (UM [0103] the firmware for the first FTL core is associated with management of the first data ) the memory device is operable to store second metadata to support a second set of flash translation layer functions, wherein the second set of flash translation layer functions is associated with management of second data stored in the second memory region. “ The memory may store firmware driven through the first and second FTL cores 120 and 130. The memory may store data required for driving of the firmware, for example, metadata . For example, the memory may operate as a working memory of the first and second FTL cores 120 and 130” (UM [0103] the firmware for the second FTL core is associated with management of the second data ) But does not explicitly state the memory device comprising a first memory region associated with a first external system and a second memory region associated with a second external system, the second memory region different from the first memory region. Hwang discloses the memory device comprising a first memory region associated with a first external system and a second memory region associated with a second external system, the second memory region different from the first memory region. “Referring to FIG. 4, the NAND flash memory device 100 may include first through third page buffers 120-1, 120-2, and 120-3, and the memory controller 200 may include first through third buffer memories 220-1, 220-2, and 220-3 ” (Hwang [0050] see Fig. 4, the buffer memories in the memory controller are associated with the respective set of memories in the NAND flash ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the buffers corresponding to individual flash memories of Hwang with the system in UM. The motivation for doing so would be to improve access latency associated with accessing flash memory for data. Regarding Claim 11 , UM and Hwang further discloses further comprising: a first port operable to couple the memory system with the first external system, wherein the first memory region and the first set of flash translation layer functions are associated with the first port; and a second port operable to couple the memory system with the second external system, wherein the second memory region and the second set of flash translation layer functions are associated with the second port. “In an embodiment, the controller 100 may include a protocol core 110, the first FTL core 120, the second FTL core 130, a common memory 140, the first memory interface 150, and the second memory interface 160 ” (UM [0052] see Fig. 2, the first memory interface/port is coupled to external memory 210 and the second memory interface/port is couple to external memory 220 ) “Referring to FIG. 4, the NAND flash memory device 100 may include first through third page buffers 120-1, 120-2, and 120-3, and the memory controller 200 may include first through third buffer memories 220-1, 220-2, and 220-3 ” (Hwang [0050] see Fig. 4, the buffer memories in the memory controller are associated with the respective set of memories in the NAND flash ) Regarding Claims 5 and 19 , UM further discloses further comprising: storing the first metadata and the first data in a first memory device of the memory system, the first memory device associated with the first external system; “ The first common memory 141 may store the first metadata transmitted from the first FTL core 120 ” (UM [0076]) “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103]) “ The memory may be configured to include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device 200 from the host device 20 or read data from the nonvolatile memory device 200 and to be transmitted to the host device 20. For example, the memory may operate as a buffer memory . The memory may be provided inside or outside the controller 100” (UM [0104]) storing third data associated with a third external system in a second memory device of the memory system, the second memory device different from the first memory device and associated with the second external system; and “Further, the first and second memory interfaces 150 and 160 may transmit write data to the nonvolatile memory device 200 or receive read data from the nonvolatile memory device 200 ” (UM [0101] see Fig. 2, it would be obvious to include a third interface to interact with the external memories in the same way as the first and second interface to improve bandwidth by promoting parallelism ) “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103] it would be obvious as a design choice to make separable the memory for storing data ) “ The memory may be configured to include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device 200 from the host device 20 or read data from the nonvolatile memory device 200 and to be transmitted to the host device 20. For example, the memory may operate as a buffer memory . The memory may be provided inside or outside the controller 100” (UM [0104]) “Referring to FIG. 4, the NAND flash memory device 100 may include first through third page buffers 120-1, 120-2, and 120-3, and the memory controller 200 may include first through third buffer memories 220-1, 220-2, and 220-3 ” (Hwang [0050] see Fig. 4, the buffer memories in the memory controller are associated with the respective set of memories in the NAND flash ) storing third metadata associated with the third data in the second memory device. “ The first common memory 141 may store the first metadata transmitted from the first FTL core 120 ” (UM [0141] the third metadata would be stored in a third common area and the location of storage in controller would be the second memory ) Regarding Claims 9, 14, and 23 , UM further discloses wherein: the first memory region comprises a first range of logical addresses within a memory device of the memory system, the first range of logical addresses associated with a first set of memory cells for storing the first data; and the second memory region comprises a second range of logical addresses within the memory device, the second range of logical addresses associated with a second set of memory cells for storing the second data. “ The file system 21 may allocate a logical block address (LBA), in which the user data is to be stored , in response to the command transmitted from the application” (UM [0034] memory cells in buffer memory would have its a range of logical addresses associated with the respective data stored in it ) “Although not shown in drawings, the data storage device 10 may further include a memory including a dynamic random access memory (DRAM) or a static random access memory (SRAM), but the memory is not limited thereto ” (UM [0103]) “ The memory may be configured to include a data buffer configured to temporarily store write data to be transmitted to the nonvolatile memory device 200 from the host device 20 or read data from the nonvolatile memory device 200 and to be transmitted to the host device 20. For example, the memory may operate as a buffer memory . The memory may be provided inside or outside the controller 100” (UM [0104]) 07-22-aia AIA Claim s 3, 4, 12, 13, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over UM (published June 02, 2022) and Hwang (published July 09, 2015) as applied to claim s 1, 10, and 15 above, and further in view of Han et al. (US 2023/0342080) (hereinafter Han) (published October 26, 2023) . Regarding Claims 3, 12, and 17 , the combination of UM and Hwang disclosed the method of claim 1, system of claim 10, and system of claim 15, but does not explicitly state further comprising: detecting a failure associated with the first metadata; and reducing a quantity of write operations to the first memory region based on the failure, and wherein a quantity of write operations to the second memory region is not reduced based on the failure being associated with the first metadata. Han discloses further comprising: detecting a failure associated with the first metadata; and “As is known in the art, a file system consistency check (FSCK) generally includes checking the consistency of a file system. If inconsistencies are found, FSCK may include interactively repairing damaged file systems (e.g., where the user decides how to fix specific problems), automatically deciding how to fix specific problems (so the user does not have to answer any questions), or reviewing the problems that need to be resolved on a file system without actually fixing them. Partially recovered files where the original file name cannot be reconstructed are typically recovered to a “lost+ found” directory that is stored at the root of the file system. To allow for FSCK, storage management process 10 may utilize one or more of the at least two reserved portions to define an FSCK tier to address data corruption in the SSD ” (Han [0058]) reducing a quantity of write operations to the first memory region based on the failure, and wherein a quantity of write operations to the second memory region is not reduced based on the failure being associated with the first metadata. “Determining 302 an operating mode of the SSD may include one or more of: determining 306 that the SSD is in normal mode; determining 308 that the SSD is in degraded mode; and determining 310 that the SSD is in recovery mode . For example, a normal mode may generally indicate the SSD is able to store new data and access stored data normally . A degraded mode may generally indicate that one or more SSDs have failed and are being rebuilt (e.g., a RAID across various SSDs or SSD slices is being rebuilt). A SSD may stay in degraded mode until the failed SSD is replaced. A recovery mode may generally indicate that a SSD has experienced data corruption (e.g., metadata corruption) and is being recovered . The SSD may switch back to normal mode when the data consistency is recovered” (Han [0056] when in recovery mode the quantity of write operations is to be reduced when compared to normal mode, each of the two memory region corresponds to different external memory accessed via different FTL and would not affect each other ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the failure detection and recovery of Han with the system in the combination of UM and Hwang. The motivation for doing so would be to improve resilience of the memory by being able to recover after being corrupted. Regarding Claim 4, 13, and 18 , Han further discloses wherein detecting the failure associated with the first set of flash translation layer functions comprises: detecting an error in a portion of the first metadata, wherein the portion of the first metadata supports the first set of flash translation layer functions. “As is known in the art, a file system consistency check (FSCK) generally includes checking the consistency of a file system. If inconsistencies are found, FSCK may include interactively repairing damaged file systems (e.g., where the user decides how to fix specific problems), automatically deciding how to fix specific problems (so the user does not have to answer any questions), or reviewing the problems that need to be resolved on a file system without actually fixing them. Partially recovered files where the original file name cannot be reconstructed are typically recovered to a “lost+ found” directory that is stored at the root of the file system. To allow for FSCK, storage management process 10 may utilize one or more of the at least two reserved portions to define an FSCK tier to address data corruption in the SSD ” (Han [0058] address data is required to support the functions of the FTL ) 07-22-aia AIA Claim s 6-8 and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over UM (published June 02, 2022) and Hwang (published July 09, 2015) as applied to claim s 1 and 15 above, and further in view of KUMAR et al. (US 2019/0250986) (hereinafter Kumar) (published August 15, 2019) . Regarding Claims 6 and 20 , the combination of UM and Hwang disclosed the method of claim 1 and system of claim 15, but does not explicitly state wherein executing the first set of flash translation layer functions comprises: generating or updating, based on the first metadata, a logical-to-physical mapping associated with the first memory region. Kumar discloses wherein executing the first set of flash translation layer functions comprises: generating or updating, based on the first metadata, a logical-to-physical mapping associated with the first memory region. “The control component 120 may drive firmware, which is referred to as a flash translation layer (FTL), to control general operations of the memory system 10. For example, the FTL may perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection , and/or bad block handling. The L2P mapping is known as logical block addressing (LBA)” (Kumar [0039]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine operations of the FTL disclosed by Kumar with the system in the combination of UM and Hwang. The motivation for doing so would be to improve performance of the flash by performing housekeeping operations to optimize the memory. Regarding Claims 7 and 21 , the combination of UM and Hwang disclosed the method of claim 1 and system of claim 15, but does not explicitly state wherein executing the first set of flash translation layer functions comprises: performing, based on the first metadata, wear levelling to distribute accesses to the first data across the first memory region. Kumar discloses wherein executing the first set of flash translation layer functions comprises: performing, based on the first metadata, wear levelling to distribute accesses to the first data across the first memory region. “The control component 120 may drive firmware, which is referred to as a flash translation layer (FTL), to control general operations of the memory system 10. For example, the FTL may perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection , and/or bad block handling. The L2P mapping is known as logical block addressing (LBA)” (Kumar [0039]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine operations of the FTL disclosed by Kumar with the system in the combination of UM and Hwang. The motivation for doing so would be to improve performance of the flash by performing housekeeping operations to optimize the memory. Regarding Claims 8 and 22 , the combination of UM and Hwang disclosed the method of claim 1 and system of claim 15, but does not explicitly state wherein executing the first set of flash translation layer functions comprises: performing, based on the first metadata, one or more garbage collection operations to delete a portion of the first data from the first memory region. Kumar discloses wherein executing the first set of flash translation layer functions comprises: performing, based on the first metadata, one or more garbage collection operations to delete a portion of the first data from the first memory region. “The control component 120 may drive firmware, which is referred to as a flash translation layer (FTL), to control general operations of the memory system 10. For example, the FTL may perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection , and/or bad block handling. The L2P mapping is known as logical block addressing (LBA)” (Kumar [0039]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine operations of the FTL disclosed by Kumar with the system in the combination of UM and Hwang. The motivation for doing so would be to improve performance of the flash by performing housekeeping operations to optimize the memory . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoon (US 2022/0269435) discloses throttling the data rate of host writes based on relationships between: host data rate being used by computer system, an internal data rate being used to transfer host write data form buffer to NAND storage, the total capacity of buffer, remaining portions of received host write data in buffer, amount of additional write data to be received, or internal throughput consumption by other components (e.g., garbage collection, error correction, data recovery, etc.) Redaelli (US 2024/0160566) discloses the corruption of FTL and in response put the memory into write-protect mode Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY LI whose telephone number is (571)270-5967. The examiner can normally be reached Monday to Friday 10:00 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.L./Examiner, Art Unit 2137 /Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137 Application/Control Number: 19/090,283 Page 2 Art Unit: 2137 Application/Control Number: 19/090,283 Page 3 Art Unit: 2137 Application/Control Number: 19/090,283 Page 4 Art Unit: 2137 Application/Control Number: 19/090,283 Page 5 Art Unit: 2137 Application/Control Number: 19/090,283 Page 6 Art Unit: 2137 Application/Control Number: 19/090,283 Page 7 Art Unit: 2137 Application/Control Number: 19/090,283 Page 9 Art Unit: 2137 Application/Control Number: 19/090,283 Page 10 Art Unit: 2137 Application/Control Number: 19/090,283 Page 11 Art Unit: 2137 Application/Control Number: 19/090,283 Page 12 Art Unit: 2137 Application/Control Number: 19/090,283 Page 13 Art Unit: 2137
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