Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/09/2025 and 2/01/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because figure 1 shows 30U and 30W incorrectly. They should be swapped in order to be correct per the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-9, 11-12, 15, and 18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hatori (JP Patent No 2013258843).
Regarding claim 1, Hatori teaches a power module (Fig. 3), comprising:
an insulating substrate (e.g. 12/14)(Fig. 3);
a first power semiconductor (e.g. 7/bottom 75)(Fig. 3 and 9) mounted on the insulating substrate;
a first conductor (e.g. 2/20/23/262)(Fig. 1, 2, and 9) at least partially overlapped with the first power semiconductor in a plan view, electrically coupled to a first terminal (e.g. collector of the bottom 75)(Fig. 9) of the first power semiconductor, and extending along a surface of the insulating substrate in a first direction (e.g. Y direction)(Fig. 1/2) (Espacenet JP2013258843 English translation, Para [0025], ” The bent portion 262 extends in the Y direction from the first extension portion 24 and is connected to the external output terminal 21”);
a current sensor (e.g. 4)(Fig. 1) which is arranged to be at least partially overlapped with or at least partially surrounded by the first conductor in the plan view, and outputs a signal corresponding to a magnitude of a magnetic field (Espacenet JP2013258843 English translation, Para [0004], ”current sensors such as Hall elements are attached to the terminal block mentioned above”) generated by a measurement current 32 flowing through the first conductor as a signal representing a current value of the measurement current (Espacenet JP2013258843 English translation, Para [0023], “The current sensor 4 transmits the measured current to the control circuit board 18, which then uses the measured current to control the switching of the semiconductor module 7”);
an encapsulating portion (e.g. 3)(Fig. 1) which encapsulates the insulating substrate, the first power semiconductor, the first conductor, and the current sensor, in a state in which the first conductor and the current sensor are insulated from each other; and
a first external terminal electrically coupled to the first conductor and exposed from the encapsulating portion (e.g. 21)(Fig. 1), wherein the current sensor is arranged between the first external terminal and the first power semiconductor in the first direction in the plan view (Fig. 1).
Regarding claim 7, Hatori teaches wherein the first power semiconductor is arranged on the first conductor (e.g. 7/70/20/2)(Fig. 1).
Regarding claim 8, Hatori teaches wherein the first conductor is provided on the insulating substrate (Espacenet JP2013258843 English translation, Para [0022], “This laminated structure 12 is fixed inside a metal frame 14. Each semiconductor module 7 is equipped with a power terminal 70. This power terminal 70 is connected to the module connection terminal 20 (see Figure 1) of the busbar 2 by welding”).
Regarding claim 9, Hatori teaches further comprising an insulating layer between the current sensor and the first conductor (Espace net JP2013258843 English translation, Para [0043], “holding portion 5 is formed on the sealing member 3 that seals the busbar 2, and the current sensor 4 is held in this holding portion 5”).
Regarding claim 11, Hatori teaches wherein the insulating layer is an insulating resin configuring the encapsulating portion (Espacenet JP2013258843 English translation, Para [0033], “The sealing member 3 is made of a synthetic resin such as PPS resin or PBT resin”).
Regarding claim 12, Hatori teaches wherein the current sensor has at least one magnetoelectric conversion element (Espacenet JP2013258843 English translation, Para [0004], “Furthermore, current sensors such as Hall elements are attached to the terminal block mentioned above”) and a signal processing IC which processes a signal output from the at least one magnetoelectric conversion element (Espacenet JP2013258843 English translation, Para [0023], “The current sensor 4 transmits the measured current to the control circuit board 18, which then uses the measured current to control the switching of the semiconductor module 7”).
Regarding claim 15, Hatori teaches wherein the at least one magnetoelectric conversion element is electrically coupled to the signal processing IC by wire bonding (Espacenet JP2013258843 English translation, Para [0004], “Furthermore, the current sensor 4 and the control circuit board 18 are connected by a wire 19”).
Regarding claim 18, Hatori teaches further comprising a second power semiconductor (e.g. 7/upper 75)(Fig. 3 and 9) having a second terminal (e.g. upper 75 emitter)(Fig. 9) electrically coupled to the first terminal (e.g. lower 75 collector/70C)(Fig. 9) of the first power semiconductor and the first conductor, a second conductor (e.g. lower conductor under 75 connecting to bottom of 81)(Fig. 9) provided on the insulating substrate and electrically coupled to a second terminal (e.g. 70b)(Fig. 9) of the first power semiconductor, a third conductor (e.g. upper conductor above 75 connecting to top of 81)(Fig. 9) provided on the insulating substrate, at least partially overlapped with the second power semiconductor in the plan view, and electrically coupled to a first terminal (e.g. 70a)(Fig. 9) of the second power semiconductor, a second external terminal (e.g. unlabeled terminal below 81 and connecting to 70b)(Fig. 9) exposed from the encapsulating portion and electrically coupled to the second conductor, and a third external terminal (e.g. unlabeled terminal above 81 and connecting to 70a)(Fig. 9) exposed from the encapsulating portion and electrically coupled to the third conductor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hatori (JP Patent No 2013258843) in view of Ngoc et. al. (DE Publication No 102023/123686 A1).
Regarding claim 10, although Hatori teaches the limitations in claims 1 and 9, Hatori does not teach wherein the insulating layer is an adhesive for bonding the current sensor and the first conductor to each other.
However, Ngoc et. al. teaches wherein the insulating layer is an adhesive (Espacenet DE102023123686 English Translation, Para [0035], “It is also advantageous if the current sensors 5 are attached to the conductors 6a, 6b 04-09-2026 alternatively or additionally by means of an additional adhesive bond”) for bonding the current sensor and the first conductor to each other.
Therefore, it would be obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to configure the “power module”
teachings of Hatori such that it comprises “wherein the insulating layer is an adhesive for bonding the current sensor and the first conductor to each other” as taught by Ngoc et. al. The reason for doing so would be to attach the current sensor to the conductor in a secure manner.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hatori (JP Patent No 2013258843) in view of Matsushita et. al. (U.S. Publication No 2024/0088797 A1).
Regarding claim 13, although Hatori teaches the limitations in claims 1 and 12, Hatori does not teach wherein the current sensor is a coreless current sensor.
However, Matsushita et. al. teaches wherein the current sensor is a coreless current sensor (Paea [0063], “The current sensor 51 is a coreless type current sensor that does not have a magnetism collecting core for converging magnetic flux”). wherein the current sensor is a coreless current sensor (Paea [0063], “The current sensor 51 is a coreless type current sensor that does not have a magnetism collecting core for converging magnetic flux”).
Therefore, it would be obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to configure the “power module”
teachings of Hatori such that it comprises “wherein the current sensor is a coreless current sensor” as taught by Matsushita et. al. The reason for doing so would be to use a current sensor that does not have a magnetism collecting core for converging magnetic flux.
Claims 14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hatori (JP Patent No 2013258843) in view of Tsujimoto (U.S. Publication No 2025/0306061 A1).
Regarding claim 14, although Hatori teaches the limitations in claims 1 and 12, Hatori does not teach wherein the current sensor is a semiconductor package in which the at least one magnetoelectric conversion element and the signal processing IC are encapsulated by a mold resin.
However, Tsujimoto teaches wherein the current sensor is a semiconductor package in which the at least one magnetoelectric conversion element and the signal processing IC are encapsulated by a mold resin (Para [0073], “The sealing portion 130 seals the magnetoelectric conversion elements 20a and 20b, the main body portion 141 of the current conductor 140, the signal processing IC 100, the wire 22, and the wire 108 with mold resin. The mold resin may be made of, for example, an epoxy-based thermosetting resin to which silica is added, and be, molded into a semiconductor package by transfer molding. Note that as described later, the sealing portion 130 may or may not seal the conductor plate that at least partially overlaps the current conductor 140 in plan view”).
Therefore, it would be obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to configure the “power module”
teachings of Hatori such that it comprises “mold resin” as taught by Tsujimoto. The reason for doing so would be to protect components from heat and environmental exposure.
Regarding claim 16, Tsujimoto teaches wherein the current sensor has two magnetoelectric conversion elements (e.g. 20a/20b)(Fig. 1A) of a longitudinal magnetic field detection type (Para [0070], “a Hall element that detects a longitudinal magnetic field of the current conductor 140 in the thickness direction is suitable as the magnetoelectric conversion elements 20a and 20b.”), and in a state in which the two magnetoelectric conversion elements are facing each other in a second direction extending along the insulating substrate and intersecting the first direction, the current sensor is arranged to be at least partially overlapped with or at least partially surrounded by the first conductor in the plan view (Para [0070], “if the magnetoelectric conversion elements 20a and 20b are arranged at positions where the magnetic field in the X axis direction is detected, a magnetoresistive element, a flux gate element, or a vertical Hall element is suitable as the magnetoelectric conversion elements 20a and 20b. More specifically, the magnetoelectric conversion elements 20a and 20b may be arranged so as to overlap the main body portion 141 of the current conductor 140 in plan view from the Z axis direction”).
Regarding claim 17, Tsujimoto teaches wherein the current sensor has at least one magnetoelectric conversion element of a transverse magnetic field detection type (Para [0163], “However, even when the magnetoelectric conversion elements 20a and 20b are transverse magnetic field sensing elements such as ferromagnetic magnetoresistive effect elements (MR), tunnel magnetoresistive elements (TMR), or vertical Hall elements, the magnetoelectric conversion elements 20a and 20b can improve the frequency characteristics on a same principle”), and the current sensor is arranged such that the at least one magnetoelectric conversion element is overlapped with the first conductor in the plan view (Fig. 1A).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hatori (JP Patent No 2013258843) in view of Matsushita et. al. (U.S. Publication No 2024/0088797 A1).
Regarding claim 19, Hatori teaches a power module comprising a plurality of the first power semiconductors (e.g. bottom 75)(Fig. 9), a plurality of the second power semiconductors (e.g. Top 75)(Fig. 9), a plurality of the first conductors (e.g. 2/20/23/262)(Fig. 1, 2, and 9).
Hatori does not teach a plurality of the current sensors.
However, Matsushita et. al. teaches a plurality of the current sensors (e.g. 51)(Fig. 1).
Therefore, it would be obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to configure the “power module”
teachings of Hatori such that it comprises “plurality of the current sensors” as taught by Matsushita et. al. The reason for doing so would be to measure current on each phase.
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Hatori teaches at least one pair of input/output terminals (e.g. 211)(Fig. 2) exposed from the encapsulating portion.
None of the prior art, taken singly or in combination, teach “at least one pair of input/output conductors which has a first portion which extends in a second direction extending along the insulating substrate and intersecting the first direction in the plan view and is electrically coupled to the current sensor, and has a second portion which is coupled to at least one of the first portion or the at least one pair of input/output terminals, and conveys a signal output from the current sensor, wherein the second portion does not overlap with”.
Claims 3-6 are indicated as allowable, as they depend on claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN W SOILEAU whose telephone number is (571)272-6650. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CT.
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/JONATHAN WALTER SOILEAU/ Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
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