CTNF 19/090,433 CTNF 83272 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 2 is objected to because of the following informalities: In claim 2, line 7, “a fourths port” should be -and a fourth port -. Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1, 6-7, and 9-12 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Huang et al. (US 7,756,123), hereafter referred to as Huang’123 . Referring to independent claim 1, Huang’123 anticipates an operating method of a device, the operating method comprising: proposing, to an external device, non-sequential numbers for respective normal lanes among a plurality of lanes (full crossbar 320 permitting arbitrary mapping of data lanes between interface 307 and interface 309 by permitting arbitrary lane order negotiation logic 330 to logically reorder lanes, see figure 3A and column 3, lines 11-17); allocating the non-sequential numbers to the respective normal lanes when receiving a positive response from the external device (wherein a PCIe controller will receive a translated version of lane numbers proposed by the other side, column 4, lines 5-6); and communicating with the external device through the normal lanes according to the non-sequential numbers allocated to the respective normal lanes (subsequent PCIe lane/link negotiation phases have an effective lane ordering that is compatible with PCIe negotiation rules, column 3, lines 33-35). As to claim 6, Huang’123 anticipates the method of claim 1, further comprising: performing a link setting operation corresponding to a configuration state on the plurality of lanes (full crossbar 320 permitting arbitrary mapping of data lanes between interface 307 and interface 309 by permitting arbitrary lane order negotiation logic 330 to logically reorder lanes, see figure 3A and column 3, lines 11-17) when a state of the link is the configuration state (link negotiation, column 3, lines 4-5). As to claim 7, Huang’123 anticipates the method of claim 1, further comprising: determining a lane number of each of the plurality of lanes through a lane number negotiation operation (arbitrary lane order negotiation logic 330 configures full crossbar 320 to achieve sequential lane ordering consistent with PCIe negotiation rules, see figure 3 and column 6, lines 20-23). As to claim 9, Huang’123 anticipates the method of claim 1, further comprising: providing ports included in the external device with a determined link number (a training set received by a particular data lane begins with a comma, a link number, and a lane number, column 3, line 67 – column 4, line 4) after determining a lane number of each of the plurality of lanes (arbitrary lane order negotiation logic 330 configures full crossbar 320 to achieve sequential lane ordering consistent with PCIe negotiation rules, see figure 3 and column 6, lines 20-23). As to claim 10, Huang’123 anticipates the method of claim 1, further comprising: providing ports included in the external device with a determined link number (a training set received by a particular data lane begins with a comma, a link number, and a lane number, column 3, line 67 – column 4, line 4) and the non-sequential numbers of the plurality of lanes by using a training sequence ordered set (PCIe utilizes training sets to negotiate lane width and ordering, column 3, lines 66-67). As to claim 11, Huang’123 anticipates the method of claim 1, further comprising: allocating the non-sequential numbers to the plurality of lanes when an accept message is received from ports included in the external device after the non-sequential numbers are provided to the ports (in subsequent training sets the lane ordering proposed by either side will be acceptable and as a result the PCIe lane rules above are satisfied, column 5, lines 39-42). As to claim 12, Huang’123 anticipates the method of claim 1, further comprising: allocating sequential lane numbers to the plurality of lanes when any accept message is not received from ports included in the external device after the non-sequential numbers are provided to the ports (a conventional LTSSM 315 built according to the current PCIe specification would see PCIe lane ordering fail, and hence link negotiation would ultimately fail; however, in accordance with the present invention, arbitrary lane order negotiation logic 330 configures full crossbar 320 to achieve a sequential lane ordering consistent with the PCIe negotiation rules, see figure 3B and column 6, lines 15-17 and 26-29) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 3-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang’123 in view of Buckland et al. (US 8,645,746), hereafter referred to as Buckland’746 . As to claim 3, Huang’123 does not appear to explicitly teach the method of claim 1, further comprising: detecting a failed lane among the plurality of lanes. However, Buckland’746 teaches detecting a failed lane among the plurality of lanes (detect failure in cable, see figure 4, step 404 and column 7, lines 23-25; one of cables 134, 136 fails, see figure 1 and column 4, lines 58-59). Huang’123 and Buckland’746 are analogous because they are drawn to the same inventive field of PCI Express link configuration. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Huang’123 and Buckland’746 before them, to modify the PCIe connection by having extra lanes configured to exchange data that would normally be transmitted on failed lanes. The motivation for doing so would have been to provide a failover mechanism in case one of the links fails (column 4, lines 56-59). Therefore, it would have been obvious to combine Huang’123 and Buckland’746 to bring about the invention as claimed. As to claim 4, Huang’123 does not appear to explicitly teach the method of claim 1, further comprising: detecting a failed lane among the plurality of lanes when a state of the link is in a detect state; and performing a link setting operation corresponding to the detect state on remaining lanes except for the failed lane among the plurality of lanes. However, Buckland’746 teaches detecting a failed lane among the plurality of lanes (one of cables 134, 136 fails, see figure 1 and column 4, lines 58-59) when a state of the link is in a detect state (detect failure in cable, see figure 4, step 404 and column 7, lines 23-25); and performing a link setting operation corresponding to the detect state on remaining lanes except for the failed lane among the plurality of lanes(if cable 136 fails, data may be exchanged using lanes within cable 134, see figure 1 and column 4, line 65 – column 5, line 1). Huang’123 and Buckland’746 are analogous because they are drawn to the same inventive field of PCI Express link configuration. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Huang’123 and Buckland’746 before them, to modify the PCIe connection by having extra lanes configured to exchange data that would normally be transmitted on failed lanes. The motivation for doing so would have been to provide a failover mechanism in case one of the links fails (column 4, lines 56-59). Therefore, it would have been obvious to combine Huang’123 and Buckland’746 to bring about the invention as claimed. As to claim 5, Buckland’746 teaches the method of claim 1, further comprising: detecting a failed lane among the plurality of lanes when a state of the link is in a polling state (one of cables 134, 136 fails, see figure 1 and column 4, lines 58-59); and performing a link setting operation corresponding to the polling state on remaining lanes except for the failed lane among the plurality of lanes (if cable 136 fails, data may be exchanged using lanes within cable 134, see figure 1 and column 4, line 65 – column 5, line 1). Huang’123 teaches the state of the link being a polling state (lane negotiation phase, column 3, lines 22-25). Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Huang’123 and Buckland’746 before them, to modify the PCIe connection by having extra lanes configured to exchange data that would normally be transmitted on failed lanes. The motivation for doing so would have been to provide a failover mechanism in case one of the links fails (column 4, lines 56-59). Therefore, it would have been obvious to combine Huang’123 and Buckland’746 to bring about the invention as claimed. As to claim 8, Huang’123 teaches the method of claim 1, further comprising: providing the non-sequential numbers of the plurality of lanes to ports (auxiliary information is stored as system BIOS (SBIOS) information that is provided to support down plugging with arbitrary lane routing, column 6, lines 36-39). Huang’123 does not appear to explicitly teach ports included in the external device. Buckland’746 teaches ports included in the external device (if cable 136 fails, data may be exchanged using lanes within cable 134, see figure 1 and column 4, line 65 – column 5, line 1; external cabling, column 4, line 50). Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Huang’123 and Buckland’746 before them, to modify the PCIe connection by having other ports which form, together with the plurality of ports, the plurality of lanes. The motivation for doing so would have been to provide a failover mechanism in case one of the links fails (column 4, lines 56-59). Therefore, it would have been obvious to combine Huang’123 and Buckland’746 to bring about the invention as claimed . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: As to claim 2, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest where the non-sequential number include: a second number, which is non-sequential to the first number, allocated to a second lane adjacent to the first lane and formed by a third port adjacent to the first port of the plurality of ports and a fourth port adjacent to the second port of the other ports. Further, it would not have been obvious to combine the above limitations with the remaining limitations of the claim, or of the antecedent claim. Zerdoum et al. (US 2016/0283299) discloses diagnostic testing of a bus at specified intervals, during times when a bus is not otherwise in use, when a fault is possible. However, this reference does not appear to anticipate or explicitly teach the subject matter determined to be allowable. Holdaway et al. (US 2009/0006889) discloses masking an inter-IC (I2C) bus failure in an I2C bus network. However, this reference does not appear to anticipate or explicitly teach the subject matter determined to be allowable . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zerdoum et al. (US 2016/0283299) discloses diagnostic testing of a bus at specified intervals, during times when a bus is not otherwise in use, when a fault is possible. Holdaway et al. (US 2009/0006889) discloses masking an inter-IC (I2C) bus failure in an I2C bus network. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.B.R/Examiner, Art Unit 2184 /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184 Application/Control Number: 19/090,433 Page 2 Art Unit: 2184 Application/Control Number: 19/090,433 Page 3 Art Unit: 2184 Application/Control Number: 19/090,433 Page 4 Art Unit: 2184 Application/Control Number: 19/090,433 Page 5 Art Unit: 2184 Application/Control Number: 19/090,433 Page 6 Art Unit: 2184 Application/Control Number: 19/090,433 Page 7 Art Unit: 2184 Application/Control Number: 19/090,433 Page 8 Art Unit: 2184 Application/Control Number: 19/090,433 Page 9 Art Unit: 2184 Application/Control Number: 19/090,433 Page 10 Art Unit: 2184 Application/Control Number: 19/090,433 Page 11 Art Unit: 2184
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