DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted 3/26/2025 is in compliance with the provisions of 37 CFR 1.97 and being considered by the examiner.
Claim Objections
Claim 14, line 5, recites “second columnar inductor,” should be --second columnar conductor--
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention.
Clam 8, lines 4-5, recites “the number of the at least one third columnar conductor is equal to or larger than the number of the at least one first columnar conductor.”
Claim 13, lines 2-3, recites “the number of the at least one third columnar conductor is equal to or larger than the number of the at least one fourth columnar conductor.”
There is insufficient antecedent basis for these terms. It is also unclear whether “the number” refers to the total number of columnar conductors, the number of particularly arranged columnar conductors or anything else. See, e.g., Specification, ¶¶156, 161, 164.
Due to the 112(b) issues noted above, no meaningful prior art examination of claims 8 and 13 is currently possible and the examiner is unable to make a meaningful prior art rejection of these claims. Note that the lack of any prior art rejection should not be construed as an indication of allowable subject matter because the patentability determination of these claims cannot be made at this time due to the ambiguity in the claim language. If and when the 112(b) issues are resolved, the examiner will conduct prior art examination and may apply prior art rejections to these claims as appropriate.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent No. 5,777,533, issued 7/7/1998 (“Kato”).
Kato discloses in Figs. 1-4 and the corresponding description:
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Claim 1
A multilayered electronic component (Figs. 3-4, annotated, multilayer substrate or laminated element 22; 3:30-5:34) comprising:
a stack including a plurality of dielectric layers stacked together (Fig. 3, annotated, Abstract, 3:42-43, multiplicity of dielectric layers 24a-24h);
a shield conductor integrated into the stack (3:49-50, 4:18-21, ground electrodes 26a and 26b formed on the bottom dielectric layer 24 in combination with external electrodes 40e and 40j formed on the side and bottom surfaces of the laminated element 22);
an inductor (Fig. 3-4, 3:57-61, pattern electrodes 34a and 36a) including at least one first columnar conductor (3:66-4:2, The other end of the pattern electrode 34a is connected to one end of the pattern electrode 36a through a via hole formed in the dielectric layer 24f.) and at least one second columnar conductor (3:64-66, One end of the pattern electrode 34a is connected to the capacitor electrode 30a through a via hole formed in the dielectric layers 24d and 24e.) each extending in a stacking direction of the plurality of dielectric layers and an inductor conductor layer connecting the at least one first columnar conductor and the at least one second columnar conductor (pattern electrodes 34a and 36a); and
at least one third columnar conductor extending in the stacking direction and connected to ground (4:2-4, The other end of the pattern electrode 36a is connected to the ground electrode 32a through a via hole formed in the dielectric layers 24e and 24f), wherein
the stack includes a first surface (bottom surface of layer 24a) and a second surface (top surface of layer 24h) located at both respective ends in the stacking direction and a first side surface (Figs. 1-3, annotated, the side surface on which a vertical/side portion of electrode 40e is arranged), a second side surface (the side surface on which a vertical/side portion of electrode 40j is arranged), a third side surface (the side surface on which electrodes 40a-d are arranged), and a fourth side surface (the side surface on which electrodes 40f-i are arranged), connecting the first surface and the second surface,
the first side surface and the second side surface are opposite to each other (Figs. 1-3),
the third side surface and the fourth side surface are opposite to each other (Figs. 1-3),
the shield conductor includes a first conductor part (Fig. 3, 4:16-22, vertical/side portion of external electrode 40e) provided to the first side surface and a second conductor part provided to the second side surface (Fig. 3, 4:16-22, external electrode 40j),
the inductor conductor layer includes a first end and a second end extending from the first side surface toward the second side surface and located at both respective longitudinal-direction ends of the inductor conductor layer (Fig. 4),
the at least one first columnar conductor is connected to a portion of the inductor conductor layer near the first end (3:64-66, One end of the pattern electrode 34a is connected to the capacitor electrode 30a through a via hole formed in the dielectric layers 24d and 24e),
the at least one second columnar conductor is connected to a portion of the inductor conductor layer near the second end (3:66-4:2, The other end of the pattern electrode 34a is connected to one end of the pattern electrode 36a through a via hole formed in the dielectric layer 24f.), and
the at least one third columnar conductor (4:2-4, The other end of the pattern electrode 36a is connected to the ground electrode 32a through a via hole formed in the dielectric layers 24e and 24f) is arranged between the inductor and the first conductor part (the via connecting the pattern electrode 36a to the ground electrode 32a is arranged between the pattern electrode 34a and the vertical/side portion of external electrode 40e).
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Claim 2
further comprising a ground conductor layer (32a) arranged in the stack and connected to the at least one third columnar conductor (4:2-4, The other end of the pattern electrode 36a is connected to the ground electrode 32a through a via hole formed in the dielectric layers 24e and 24f).
Claim 3
wherein the ground conductor layer (32a) is arranged between the inductor (34a/36a) and the first surface (24a).
Claim 4
wherein part of the ground conductor layer overlap at least part of the inductor when seen in one direction parallel to the stacking direction (Figs. 3-4, ground conductor layer 32a overlaps inductor 34a/36a).
Claim 5
wherein the shield conductor further includes a third conductor part provided to the first surface (Fig. 3, annotated, bottom portion of electrode 40e).
Claim 6
further comprising another inductor (Figs. 3-4, 34b/36b) including two columnar conductors each extending in the stacking direction and a conductor layer connecting the two columnar conductors (3:57-4:12), wherein
the ground conductor layer (32a) does not overlap the other inductor (34b/36b) when seen In one direction parallel to the stacking direction (Figs. 3-4).
Claim 14
A multilayered electronic component (Figs. 3-4, multilayer substrate or laminated element 22; 3:30-5:34) comprising:
a stack including a plurality of dielectric layers stacked together (Fig. 3, annotated, Abstract, 3:42-43, multiplicity of dielectric layers 24a-24h);
a shield conductor integrated into the stack (3:49-50, 4:18-21, ground electrodes 26a and 26b formed on the bottom dielectric layer 24 in combination with external electrodes 40e and 40j formed on the side and bottom surfaces of the laminated element 22);
an inductor (Fig. 3-4, 3:57-61, pattern electrodes 34a and 36a) including at least one first columnar conductor (3:66-4:2, The other end of the pattern electrode 34a is connected to one end of the pattern electrode 36a through a via hole formed in the dielectric layer 24f.) and at least one second columnar conductor (3:64-66, One end of the pattern electrode 34a is connected to the capacitor electrode 30a through a via hole formed in the dielectric layers 24d and 24e.) each extending in a stacking direction of the plurality of dielectric layers and an inductor conductor layer connecting the at least one first columnar conductor and the at least one second columnar conductor (pattern electrodes 34a and 36a); and a ground conductor layer (32a) connected to ground (3:56-57), wherein
the stack includes a first surface (bottom surface of layer 24a) and a second surface (top surface of layer 24h) located at both respective ends in the stacking direction (Figs. 3-4),
the shield conductor includes a conductor part provided to the first surface (Fig. 3, 4:16-22, vertical/side portion of external electrode 40e), and
the ground conductor layer (32a) is arranged between the inductor (34a/36a) and the conductor part (Figs. 3-4).
Allowable Subject Matter
Claims 7, 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2022/0294411, published 9/15/2022 (“Sato”) discloses a multilayer triplexer including a common port, three signal ports, three signal paths, three filters each with at least one inductor disposed in respective regions, three structure bodies with sub-structure bodies including via and connecting conductor layers (Figs. 1-11, ¶¶37-98)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR COLE, telephone number (571) 272-4686. The examiner can be reached Monday-Friday, 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA LINDGREN BALTZELL, can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/VICTOR COLE/
Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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