Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0059479, filed on 03 May 2024.
Information Disclosure Statement
The information disclosure statement filed 05 June 2025 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because Foreign Patent Document KR 1980010449 U information listed in Information Disclosure Statement does not comply provided document and The Office Action for Korean Application did not provide any translation for the summary of the decision. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “520” has been used to designate both operation for obtaining an input #N measurement value and operation for comparing if the measurement value is larger than the upper limit value for input #N value. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Reference number 30 from Fig.1
Reference number 620 from Fig. 6
Reference numbers 710, 720, and 730 from Fig. 7
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0054], line 3, “random access memory” should read “random-access memory”
In paragraph [00138[, line 7, “random access memory(RAM)” should read “random-access memory (RAM)”
Appropriate correction is required.
Claim Objections
Claim 19 objected to because of the following informalities: It is unclear if claim 19 is independent claim or dependent claim of claim 1. For the purpose of the examination, claim 19 is considered as a dependent claim of claim 1. If claim 19 is an independent claim, examiner suggests Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite in that it fails to point out what is included or excluded by the claim language. This claim is an omnibus type claim.
Claim 1 recites “determine a presence or absence of a first error in the digital, based on a storage position” in line 5-6. Claim 3 further recites that the determination is based on “whether the channel selection signal and the storage position of the data correspond to each other” in line 3-4. The wording of the claim implies the comparison between channel signal and the storage position of the data. However, in paragraph [0072] – [0073], the specification teaches using preset DC voltage as input data for the first error checking. This appears to indicate the comparison of expected digital data and the stored digital data. This contradicts with the claim language. For the purpose of the examination, this step will be considered as comparing the expected digital data, based on channel selection signal, and the stored digital data.
Claim 2, 4-9, and 19, which are dependent on claim 1, are similarly rejected
Claim 10 recites “determine a presence or absence of a first error in the digital, based on a storage position” in line 8-9. Claim 12 further recites that determination is based on “whether the channel selection signal and the storage position of the data correspond to each other” in line 3-4. These claim languages have same issues as claim 1 and 3. For the purpose of the examination, this step will be considered as comparing the expected digital data and the stored digital data in the storage position according to the channel selection signal.
Claim 11 and 13-18, which are dependent on claim 10, are similarly rejected.
Claim 19 recites both an apparatus and a process of using the apparatus. When both an apparatus and a method are claim in same claim it is unclear whether infringement occurs when the apparatus is constructed or when apparatus is used. Therefore, the scope of the claim is indefinite.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-19 rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
As per claim 1:
At Step 1:
The claim is directed to a "method" and thus directed to a statutory category
At Step 2A, Prong One:
The claim recites the following limitations directed to an abstract idea:
“determining a presence or absence of a first error in the digital data, based on a storage position of the digital data; determining a presence or absence of a second error in the digital data, based on a comparison between the digital data and a preset threshold value", as drafted this recites a mentally performable process as an evaluation or judgment. One can mentally evaluate or judge if an error has occurred by comparing the digital data to expected digital data and comparing digital to the preset threshold value.
“determining an error of at least one of the multiplexer or the A/D converter, based on the presence or absence of the first error and the presence or absence of the second error “, as drafted this recites a mentally performable process as an evaluation or judgement. One can mentally evaluate or judge the error multiplexer or the A/D converter based on the result of two error tests.
At Step 2A, Prong Two:
The claim recites the following additional elements:
That the method is “selecting input data corresponding to a channel selection signal, based on a multiplexer, and generating digital data by converting the input data into a digital form, based on an analog-to-digital (A/D) converter” which is a mere data gathering using generic computer components and represents mere instruction apply on a computer as in MPEP 2106.05(f), which does not provide integration into a practical application.
“wherein the input data comprises a preset direct current voltage” recites insignificant extra-solution activity as mere data selection and does not limit the data gathering as identified in MEP 2106.05(g) and does not provide integration into a practical application.
At Step 2B:
The conclusions for the mere implementation using a computer are carried over and do not provide significantly more.
With respect to “selecting…” above identified as mere data gathering using generic computer components (multiplexer and A/D converter) above, when re-evaluated these elements are well-understood, routine, and conventional as evidenced by the court case, Berkheimer v. HP, Inc. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. The Federal Circuit determined that these claims were directed to mental processes of parsing and comparing data, because the steps were recited at a high level of generality and merely used computers as a tool to perform the processes. 881 F.3d at 1366, 125 USPQ2d at 1652-53. See MPEP 2106.05(a).
Looking at the claim as a whole does not change this conclusion and the claim is ineligible.
As per claim 10:
At Step 1:
The claim is directed to a "machine" and thus directed to a statutory category
At Step 2A, Prong One:
The claim recites the following limitations directed to an abstract idea:
“determining a presence or absence of a first error in the digital data, based on a storage position of the digital data; determining a presence or absence of a second error in the digital data, based on a comparison between the digital data and a preset threshold value", as drafted this recites a mentally performable process as an evaluation or judgment. One can mentally evaluate or judge if an error has occurred by comparing the digital data to expected digital data and comparing digital to the preset threshold value.
“determining an error of at least one of the multiplexer or the A/D converter, based on the presence or absence of the first error and the presence or absence of the second error “, as drafted this recites a mentally performable process as an evaluation or judgement. One can mentally evaluate or judge the error multiplexer or the A/D converter based on the result of two error tests.
At Step 2A, Prong Two:
The claim recites the following additional elements:
That the machine comprises “at least one memory; and at least one processor, wherein the at least one processor is configured to…” which is a high-level recitation of a generic computer components and represents mere instructions to apply on a computer as in MPEP 2106.05(f), which does not provide integration into a practical application.
“selecting input data corresponding to a channel selection signal, based on a multiplexer, and generating digital data by converting the input data into a digital form, based on an analog-to-digital (A/D) converter” which is a mere data gathering using generic computer components and represents mere instruction apply on a computer as in MPEP 2106.05(f), which does not provide integration into a practical application.
“wherein the input data comprises a preset direct current voltage” recites insignificant extra-solution activity as mere data selection and does not limit the data gathering as identified in MEP 2106.05(g) and does not provide integration into a practical application.
At Step 2B:
The conclusions for the mere implementation using a computer are carried over and does not provide significantly more.
With respect to “selecting…” above identified as mere data gathering using generic computer components (multiplexer and A/D converter) above, when re-evaluated these elements are well-understood, routine, and conventional as evidenced by the court case, Berkheimer v. HP, Inc. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. The Federal Circuit determined that these claims were directed to mental processes of parsing and comparing data, because the steps were recited at a high level of generality and merely used computers as a tool to perform the processes. 881 F.3d at 1366, 125 USPQ2d at 1652-53. See MPEP 2106.05(a).
Looking at the claim as a whole does not change this conclusion and the claim is ineligible.
Dependent claims 2-9, and 11-19 are extend elements of abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes and Mathematical Concepts. The dependent claims do not avoid any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstract idea. Therefore, the dependent claims are not patent eligible.
As per claim 19:
The claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim recites “computer-readable recording medium” which can be a carrier wave covers a non-statutory embodiment. In Mentor Graphics v. EVE-USA, Inc., in which the patentee claimed a “machine-readable medium.” The court determined these claims are non-statutory, because their scope encompasses both statutory random-access memory and non-statutory carrier waves. 851 F.3d at 1294-95, 112 USPQ2d at 1134. See MPEP 2106.03(II).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 10-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Itagaki (JP 2011134174 A), hereinafter “Itagaki”.
As per claim 1, Itagaki teaches a method comprising: selecting input data corresponding to a channel selection signal, based on a multiplexer (“multiplexers 11 and 12 select one of the signals applied to input terminals IN1 to IN4 based on the 2-bit selection signal input” Itagaki paragraph 4), and
generating digital data by converting the input data into a digital form, based on an analog-to-digital (A/D) converter (“The output signals of the multiplexers 11 and 12 are input to the programmable gain amplifiers 13 and 14, respectively. The programmable gain amplifiers 13 and 14 are amplifiers that can set a gain, multiply the input signal by a set gain, and output the signal to the analog-to-digital converter 15.” Itagaki paragraph 7);
determining a presence or absence of a first error in the digital data, based on a storage position of the digital data (“Next, the diagnosis operation unit 23 outputs selection signals “00”, “10”, and “11” in this order. The output digital values of the analog-digital converter 15 are the reference voltages RefA, RefB, and 0, respectively. The diagnostic operation unit 23 evaluates these digital values, and determines that the reference voltage RefA, RefB or the signal input circuit 10 is abnormal if it is out of the range.” Itagaki paragraph 11);
determining a presence or absence of a second error in the digital data, based on a comparison between the digital data and a preset threshold value (“First, the diagnostic operation unit 23 outputs a selection signal “01”. The multiplexers 11 and 12 select the input signals + and −, and the analog / digital converter 15 converts the difference between the input signals to a digital value and outputs the digital value to the diagnosis unit 20. The diagnosis operation unit 23 determines that the input signal (input signal +, input signal −) is abnormal when the input digital value is out of the range.” Itagaki paragraph 10); and
determining an error of at least one of the multiplexer or the A/D converter, based on the presence or absence of the first error and the presence or absence of the second error (Itagaki Paragraph 10 and 11. Itagaki’s invention determines the error based on range first, then determines the error based on comparison of expected digital data and the actual digital data. The order of error checking does not have significance as claimed invention mentions that “The expression “first,” “second,” […] do not limit the order and/or importance of the components.” In Paragraph [0026]),
wherein the input data comprises a preset direct current voltage (“The reference voltage RefA, the input signal +, the reference voltage RefB, and the ground potential GND are input to the input terminals IN1 to IN4 of the multiplexer 11” Itagaki Paragraph 5).
As per claim 2, Itagaki teaches the method of claim 1, wherein the input data comprises at least one of: first input data comprising at least one of an alternating current voltage or a direct current voltage; and second input data comprising a direct current voltage set to be different from the first input data (“it is also possible to increase the number of input terminals to which input signals are input and to input two or more types of input signals.” Itagaki Paragraph 59).
As per claim 3, Itagaki teaches the method of claim 1, wherein the determining of the presence or absence of the first error comprises determining the presence or absence of the first error in the digital data, based on whether the channel selection signal and the storage position of the digital data correspond to each other (“Next, the diagnosis operation unit 23 outputs selection signals “00”, “10”, and “11” in this order. The output digital values of the analog-digital converter 15 are the reference voltages RefA, RefB, and 0, respectively. The diagnostic operation unit 23 evaluates these digital values, and determines that the reference voltage RefA, RefB or the signal input circuit 10 is abnormal if it is out of the range.” Itagaki Paragraph 11).
As per claim 4, Itagaki teaches the method of claim 1, wherein the determining of the presence or absence of the second error comprises: setting an upper limit value and a lower limit value for the input data (“The input signal + and the input signal − mean the positive side and the negative side of the differential input signal.” Itagaki paragraph 6); and
determining the presence or absence of the second error in the digital data, based on whether the digital data satisfies a range between the upper limit value and the lower limit value (Itagaki Paragraph 10).
As per claim 10, Itagaki teaches an apparatus comprising: at least one memory; and at least one processor, wherein the at least one processor is configured (“The diagnosis unit 40 is constituted by a microprocessor, and the diagnosis operation unit 43 is realized by software operating on the microprocessor.” Itagaki paragraph 29; Microprocessor includes memories) to:
selecting input data corresponding to a channel selection signal, based on a multiplexer (“multiplexers 11 and 12 select one of the signals applied to input terminals IN1 to IN4 based on the 2-bit selection signal input terminal SEL, and output this selected signal to the output terminal OUT.” Itagaki paragraph 4), and
generating digital data by converting the input data into a digital form, based on an analog-to-digital (A/D) converter (“The output signals of the multiplexers 11 and 12 are input to the programmable gain amplifiers 13 and 14, respectively. The programmable gain amplifiers 13 and 14 are amplifiers that can set a gain, multiply the input signal by a set gain, and output the signal to the analog-to-digital converter 15.” Itagaki paragraph 7);
determining a presence or absence of a first error in the digital data, based on a storage position of the digital data (“the diagnosis operation unit 23 outputs selection signals “00”, “10”, and “11” in this order. The output digital values of the analog-digital converter 15 are the reference voltages RefA, RefB, and 0, respectively. The diagnostic operation unit 23 evaluates these digital values, and determines that the reference voltage RefA, RefB or the signal input circuit 10 is abnormal if it is out of the range.” Itagaki paragraph 11);
determining a presence or absence of a second error in the digital data, based on a comparison between the digital data and a preset threshold value (“the diagnostic operation unit 23 outputs a selection signal “01”. The multiplexers 11 and 12 select the input signals + and −, and the analog / digital converter 15 converts the difference between the input signals to a digital value and outputs the digital value to the diagnosis unit 20. The diagnosis operation unit 23 determines that the input signal (input signal +, input signal −) is abnormal when the input digital value is out of the range.” Itagaki paragraph 10); and
determining an error of at least one of the multiplexer or the A/D converter, based on the presence or absence of the first error and the presence or absence of the second error (Itagaki Paragraph 10 and 11. Itagaki’s invention determines the error based on range first, then determines the error based on comparison of expected digital data and the actual digital data. The order of error checking does not have significance as claimed invention mentions that “The expression “first,” “second,” […] do not limit the order and/or importance of the components.” In Paragraph [0026]),
wherein the input data comprises a preset direct current voltage (“The reference voltage RefA, the input signal +, the reference voltage RefB, and the ground potential GND are input to the input terminals IN1 to IN4 of the multiplexer 11” Itagaki Paragraph 5).
As per claim 11, Itagaki teaches the apparatus of claim 10, wherein the input data comprises at least one of: first input data comprising at least one of an alternating current voltage or a direct current voltage; and second input data comprising a direct current voltage set to be different from the first input data (“ it is also possible to increase the number of input terminals to which input signals are input and to input two or more types of input signals.” Itagaki Paragraph 59).
As per claim 12, Itagaki teaches the apparatus of claim 10, wherein the at least one processor is further configured to determine the presence or absence of the first error in the digital data, based on whether the channel selection signal and the storage position of the digital data correspond to each other (Itagaki Paragraph 11).
As per claim 13, Itagaki teaches the apparatus of claim 10, wherein the at least one processor is further configured to: set an upper limit value and a lower limit value for the input data (“The input signal + and the input signal − mean the positive side and the negative side of the differential input signal.” Itagaki paragraph 6); and
determining the presence or absence of the second error in the digital data, based on whether the digital data satisfies a range between the upper limit value and the lower limit value (Itagaki Paragraph 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences b
tween the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5, 6, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki in view of Bae (KR 19960027898 A), hereinafter "Bae".
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki in view of Rami Mooti (Designing with Multiple Multiplexers in Series: A Guide to Cascading Multiplexers, January 2024, Texas Instruments) hereinafter, Mooti.
Claim(s) 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki in view of Sunter et al. (US 5659312 A), hereinafter “Sunter”.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki in view of Sunter and further view of Mooti.
As per claim 5, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value, setting upper and lower limit value for the input data, and determining the error of the digital data based on whether the digital data satisfies the range between the upper and lower limit values. See 35 U.S.C. 102 rejections for claim 1 and claim 4 for further details.
Itagaki does not teach “the method of claim 4, wherein the upper limit value and the lower limit value are calculated based on a first error of at least one of a resistor or an integrated circuit (IC) element existing in a circuit comprising the multiplexer and the A/D converter and a second error of an analog-to-digital conversion (ADC) unit comprising the multiplexer and the A/D converter.”
However, Bae, in an analogous art, teaches wherein the upper limit value and the lower limit value are calculated based on a first error of at least one of a resistor or an integrated circuit (IC) element existing in a circuit comprising the multiplexer and the A/D converter and a second error of an analog-to-digital conversion (ADC) unit comprising the multiplexer and the A/D converter (“Comparing unit 150 for determining whether the output of the 140 is included within the prescribed reference value, and detecting the output change of the comparator 150 to count the number of changes The second count circuit unit 160 and a data comparator 120 for outputting PASS and FAIL signals by comparing the final count result and the expected value in the second count circuit unit 160.” Bae Paragraph 12)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to use predetermined reference value as the upper limit value and the lower limit value for checking the error, as disclosed by Bae.
Furthermore, one skilled in the art would have been motivated by Bae to use predetermined or calculated value based on the circuit components over using differential input signal as Bae teaches determining the voltage range of the input based on the characteristic of the circuit component (“The analog / digital converter 101 is a 4-bit analog / digital converter 101. It is assumed that the input voltage ranges from 0V to 5V” Bae Paragraph 17).
As per claim 6, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, and determine the error based on the comparison of stored digital data and expected digital data, and determine the error based on the comparison between the digital data and the preset threshold value. See the 35 U.S.C. 102 rejections for claim 1 for further details. same as above
Itagaki does not teach “, wherein the determining of the presence or absence of the second error comprises: calculating a count in which the digital data deviates from the preset threshold value; and determining the presence or absence of the second error in the digital data, based on a comparison between the count and a threshold count set based on the input data.”
However, Bae, in an analogous art, teaches wherein the determining of the presence or absence of the second error comprises: calculating a count in which the digital data deviates from the preset threshold value; and determining the presence or absence of the second error in the digital data, based on a comparison between the count and a threshold count set based on the input data (Bae Paragraph 12).
Therefore, it would have been obvious for one in skill in the art to before effective filing date of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to the presence or absence of the error in the digital data, based on a comparison between the count and a threshold count set based on the input data, as disclosed by Bae.
Furthermore, one skilled in the art would have been motivated by teaching of Bae that his invention improved reliability and account the noise (“the present invention enables the conversion characteristic test of the analog / digital converter 101 according to the change of the two output bits of the output LSB of the analog / digital converter 101 so that the test circuit operates more concisely and reliably. There is an effect that can be done. In addition, four counters are used to test from the first point of output N to the output change of N + 2 at the time of each code output, so that the test takes into account the conversion noise generated during conversion.” Bae paragraph 54-55)
As per claim 7, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, and determine the error based on the comparison of stored digital data and expected digital data, and determine the error based on the comparison between the digital data and the preset threshold value. See the 35 U.S.C. 102 rejections for claim 1 for further details.
Itagaki does not teach “The method of claim 1, further comprising selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
However, a Mooti teaches the method of claim 1, further comprising selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer (Mooti Figure 1-1 and Figure 2-3).
Therefore, it would have been obvious for one with skill in the art before the effective filing date of claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to have select the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer, as disclosed by Mooti.
Furthermore, one skilled in the art would have been motivated by the teaching of Mooti that implementing the claimed additional multiplexer will allow having more inputs connected to single output (“smaller multiplexers create a larger multiplexer with a greater number of inputs feeding into the eventual single output.” Mooti, Introduction, Paragraph 2, line 1-2).
As per claim 8, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, and determine the error based on the comparison of stored digital data and expected digital data, and determine the error based on the comparison between the digital data and the preset threshold value. See the 35 U.S.C. 102 rejections for claim 1 for further details.
Itagaki does not teach “generating the input data by converting the digital data into an analog form, based on a digital-to-analog (D/A) converter.”
However, Sunter, in analogous art, teaches the method of generating the input data by converting the digital data into an analog form, based on a digital-to-analog (D/A) converter (DAC 20 in Fig. 2 and Fig. 3, Sunter).
Therefore, it would have been obvious for one with skill in the art to before effective filing date of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to include generating the input data by converting the digital data into an analog form, based on a digital-to-analog converter, as disclosed by Sunter.
Furthermore, one skilled in the art would have been motivated by the teaching of Sunter that implementing the claimed digital-to-analog converter allow generate test input from the same processing unit (“A conventional binary counter-based circuit which is part of the logic BIST controller 40, generates a test pattern which is applied to the ADC 14 via the DAC 20. The output of the DAC 20 is disabled from driving the normal analog outputs in the test mode. The ADC 14 output signal (response) is accumulated in a register and/or is compared to the input test pattern and the difference is accumulated in a register” Sunter Col. 4, line 23-30).
As per claim 9, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, and determine the error based on the comparison of stored digital data and expected digital data, and determine the error based on the comparison between the digital data and the preset threshold value. See the 35 U.S.C. 102 rejections for claim 1 for further details.
Itagaki does not teach “The method of claim 1, further comprising: generating the input data by converting the digital data into an analog form, based on a D/A converter; and selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
However, Sunter, in an analogous art, teaches the method of claim 1, further comprising: generating the input data by converting the digital data into an analog form, based on a D/A converter (DAC 20 in Fig. 2 and Fig. 3, Sunter), but it fails to teach “selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
Alternatively, Mooti teaches the selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer (Mooti Figure 1-1 and Figure 2-3).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to include generating the input data by converting the digital data into an analog form, based on a digital-to-analog converter, and selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.
Furthermore, one skilled in at the would have been motivated by teaching of Sunter, and Mooti that implementing the claimed digital-to-analog converter allow generate test input from the same processing unit (Sunter Col. 4, line 23-30) and additional multiplexer will allow having more inputs connected to single output (Mooti, Introduction, Paragraph 2, line 1-2).
As per claim 14, Itagaki teaches the apparatus comprising at least one memory and at least one processor, wherein the at least one processor is configured to: selecting input signal corresponding to the channel selection signal, based on a multiplexer, generate digital data by converting input data using the A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value, setting upper and lower limit value for the input data, and determining the error of the digital data based on whether the digital data satisfies the range between the upper and lower limit values. See 35 U.S.C. 102 rejections for claim 10 and claim 13 for further details
Itagaki does not teach “The apparatus of claim 13, wherein the upper limit value and the lower limit value are calculated based on a first error of at least one of a resistor or an integrated circuit (IC) element existing in a circuit comprising the multiplexer and the A/D converter and a second error of an ADC unit comprising the multiplexer and the A/D converter.”
However, Bae, in an analogous art, teaches the apparatus of claim 13, wherein the upper limit value and the lower limit value are calculated based on a first error of at least one of a resistor or an integrated circuit (IC) element existing in a circuit comprising the multiplexer and the A/D converter and a second error of an ADC unit comprising the multiplexer and the A/D converter (“Comparing unit 150 for determining whether the output of the 140 is included within the prescribed reference value, and detecting the output change of the comparator 150 to count the number of changes The second count circuit unit 160 and a data comparator 120 for outputting PASS and FAIL signals by comparing the final count result and the expected value in the second count circuit unit 160.” Bae Paragraph 12).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to use predetermined reference value as the upper limit value and the lower limit value for checking the error, as disclosed by Bae.
Furthermore, one skilled in the art would have been motivated by Bae to use predetermined or calculated value based on the circuit components over using differential input signal as Bae teaches determining the voltage range of the input based on the characteristic of the circuit component (“The analog / digital converter 101 is a 4-bit analog / digital converter 101. It is assumed that the input voltage ranges from 0V to 5V” Bae Paragraph 17).
As per claim 15, Itagaki teaches the apparatus comprising at least one memory and at least one processor, wherein the at least one processor is configured to: selecting input signal corresponding to the channel selection signal, based on a multiplexer, generate digital data by converting input data using the A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value. See 35 U.S.C. 102 rejections for claim 10 for further details.
Itagaki does not teach “The apparatus of claim 10, wherein the at least one processor is further configured to: calculate a count in which the digital data deviates from the preset threshold value; and determine the presence or absence of the second error in the digital data, based on a comparison between the count and a threshold count set based on the input data.”
However, Bae, in an analogous art, teaches the apparatus of claim 10, wherein the at least one processor is further configured to: calculate a count in which the digital data deviates from the preset threshold value; and determine the presence or absence of the second error in the digital data, based on a comparison between the count and a threshold count set based on the input data (Bae Paragraph 12).
Therefore, it would have been obvious for one with skill in the art to before effective filing date of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to the presence or absence of the error in the digital data, based on a comparison between the count and a threshold count set based on the input data, as disclosed by Bae.
Furthermore, one skilled in the art would have been motivated by teaching of Bae that his invention improved reliability and account the noise (“the present invention enables the conversion characteristic test of the analog / digital converter 101 according to the change of the two output bits of the output LSB of the analog / digital converter 101 so that the test circuit operates more concisely and reliably. There is an effect that can be done. In addition, four counters are used to test from the first point of output N to the output change of N + 2 at the time of each code output, so that the test takes into account the conversion noise generated during conversion.” Bae paragraph 54-55).
As per claim 16, Itagaki teaches the apparatus comprising at least one memory and at least one processor, wherein the at least one processor is configured to: selecting input signal corresponding to the channel selection signal, based on a multiplexer, generate digital data by converting input data using the A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value. See 35 U.S.C. 102 rejections for claim 10 for further details.
Itagaki does not teach “The apparatus of claim 10, wherein the at least one processor is further configured to select the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
However, Mooti teaches the apparatus of claim 10, wherein the at least one processor is further configured to select the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer. (Mooti, Figure 1-1 and Figure 2-3).
Therefore, this application can be done and would have been obvious for one with skill in the art before the effective filing date of claimed invention to have modified the apparatus of determining an error of multiplexer or A/D converter disclosed by Itagaki, to have select the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer, as disclosed by Mooti.
Furthermore, one skilled in the art would have been motivated by the teaching of Mooti that implementing the claimed additional multiplexer will allow having more inputs connected to single output (“smaller multiplexers create a larger multiplexer with a greater number of inputs feeding into the eventual single output.” Mooti Introduction, Paragraph 2, line 1-2).
As per claim 17, Itagaki teaches the apparatus comprising at least one memory and at least one processor, wherein the at least one processor is configured to: selecting input signal corresponding to the channel selection signal, based on a multiplexer, generate digital data by converting input data using the A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value. See 35 U.S.C. 102 rejections for claim 10 for further details.
Itagaki does not teach “The apparatus of claim 10, wherein the at least one processor is further configured to generate the input data by converting the digital data into an analog form, based on a digital-to-analog (D/A) converter.”
However, Sunter, in an analogous art, teaches the apparatus of claim 10, wherein the at least one processor is further configured to generate the input data by converting the digital data into an analog form, based on a digital-to-analog (D/A) converter (DAC 20 in Fig. 2 and Fig. 3, Sunter).
Therefore, it would have been obvious for one with skill in the art to before effective filing date of the claimed invention to have modified the apparatus of determining an error of multiplexer or A/D converter disclosed by Itagaki, to include generating the input data by converting the digital data into an analog form, based on a digital-to-analog converter, as disclosed by Sunter.
Furthermore, one skilled in the art would have been motivated by the teaching of Sunter that implementing the claimed digital-to-analog converter allow generate test input from the same processing unit (“A conventional binary counter-based circuit which is part of the logic BIST controller 40, generates a test pattern which is applied to the ADC 14 via the DAC 20. The output of the DAC 20 is disabled from driving the normal analog outputs in the test mode. The ADC 14 output signal (response) is accumulated in a register and/or is compared to the input test pattern and the difference is accumulated in a register” Sunter Col. 4, line 23-30).
As per claim 18, Itagaki teaches the apparatus comprising at least one memory and at least one processor, wherein the at least one processor is configured to: selecting input signal corresponding to the channel selection signal, based on a multiplexer, generate digital data by converting input data using the A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value. See 35 U.S.C. 102 rejections for claim 10 for further details.
Itagaki does not teach “The apparatus of claim 10, wherein the at least one processor is further configured to: generate the input data by converting the digital data into an analog form, based on a D/A converter; and select the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
However, Sunter, in an analogous art, teaches the apparatus of claim 10, further comprising: generating the input data by converting the digital data into an analog form, based on a D/A converter (DAC 20 in Fig. 2 and Fig. 3, Sunter), but it fails to teach “selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.”
Alternatively, Mooti teaches the selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer (Mooti, Figure 1-1 and Figure 2-3).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of determining an error of multiplexer or A/D converter disclosed by Itagaki, to include generating the input data by converting the digital data into an analog form, based on a digital-to-analog converter, and selecting the input data corresponding to the channel selection signal, based on an additional multiplexer, wherein the input data is output from an output terminal of the additional multiplexer and input to an input terminal of the multiplexer.
Furthermore, one skilled in at the would have been motivated by teaching of Sunter, and Mooti that implementing the claimed digital-to-analog converter allow generate test input from the same processing unit (Sunter Col. 4, line 23-30) and additional multiplexer will allow having more inputs connected to single output (Mooti, Introduction, Paragraph 2, line 1-2).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki inview of Kim (KR 20210028398 A), hereinafter “Kim”.
As per claim 19, Itagaki teaches the method comprising selecting input data based on channel selection signal on a multiplexer, convert to digital data using A/D converter, determine the error based on the comparison of stored digital data and expected digital data, determine the error based on the comparison between the digital data and the preset threshold value, setting upper and lower limit value for the input data, and determining the error of the digital data based on whether the digital data satisfies the range between the upper and lower limit values. See 35 U.S.C. 102 rejections for claim 1 for further details.
Itagaki does not teach “A computer-readable recording medium having recorded thereon a program for causing a computer to perform the method of claim 1.”
However, Kim, in an analogous art, teaches the computer-readable recording medium having recorded thereon a program for causing a computer to perform the method of claim 1 (“In addition, such a computer program is stored in a computer readable media” Kim, Paragraph [0054]).
Therefore, it would be obvious for one with skill in the art before the effective filing date of the claimed invention to have modified the method of determining an error of multiplexer or A/D converter disclosed by Itagaki, to include computer-readable recording medium having recorded thereon a program for causing a computer to perform the error checking method.
Furthermore, one skilled in the art would have been motivated by the teaching of Kim that implementing computer readable recording media allows the execution of claimed invention in computer (Kim, Paragraph [0054])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20050248477 A1 teaches analog-to-digital converter with range error detection. It uses a multiplexer to allow multiple signal and channel selection, an analog-to-digital converter to convert the analog data to digital data, and a processor to compare a sequence of digital outputs to a sequence of normal ranges.
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/J.J./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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