DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: “internal operating clock” should read –the first internal operating clock--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 6 states “wherein a minimum value of the first frequency range is a value decreased from a second frequency by a first ratio, and wherein a maximum value of the first frequency range is a value increased from the second frequency by the first ratio.” Paragraphs 95-98 show the second frequency decreasing or increasing from the first frequency. Nowhere does the specification state anything about a minimum value, maximum value or a first ratio.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 3, 7, 12, 13, 15 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 5, 10, 12, 14 and 17 of U.S. Patent No. 12283251. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims correspond as follows:
Application No. 19/090751
Patent No. 12283251
Claim 2
Claims 1, 12 and 14
Claim 3
Claim 17
Claim 7
Claim 10
Claim 12
Claim 4
Claim 13
Claim 5
Claim 15
Claims 1 and 4
Claim 21
Claims 14 and 17
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ansari et al. (US 2019/0325844) in view of Brijesh (US 2014/0168233).
In regard to claim 2, Ansari et al. teach a system on chip (SoC) (paragraph 15) comprising: a clock generator configured to generate a first internal operating clock; and a control circuit configured to generate and output frame data based on internal operating clock output from the clock generator (fig. 2 and paragraph 36. Ansari et al. shows outputting frame data at certain timings. This must be accomplished with a clock) but does not teach wherein the control circuit is configured to: receive a frame data request signal from a display panel via a side link, transmit first frame data, which is generated based on the first internal operating clock, to the display panel via a main link, receive a sync request signal from the display panel via the side link, and in response to the sync request signal, transmit a first frequency signal, which is generated based on the first internal operating clock, to the display panel.
Brijesh teaches wherein the control circuit is configured to: receive a frame data request signal from a display panel via a side link (paragraph 98, sink processor transmits first sync signal to source via auxiliary link), transmit first frame data, which is generated based on the first internal operating clock (paragraph 99, first sync signal used as input to PLL to generate a second sync signal), to the display panel via a main link (paragraph 100, transmit video data via main link), receive a sync request signal from the display panel via the side link, and in response to the sync request signal, transmit a first frequency signal, which is generated based on the first internal operating clock, to the display panel (paragraphs 98-100. Brijesh shows the sink device sending a sync signal to the source device via a side link. Upon reception of this signal., paragraph 100 of Brijesh shows the source device sending a vertical sync signal).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh because the synchronization signals of Brijesh would allow the device to enter PSR mode while saving power.
In regard to claim 3, Brijesh teaches wherein the side link includes a low- bandwidth communication link, and wherein the main link includes a high-bandwidth communication link (paragraph 20).
In regard to claim 4, Brijesh teaches wherein the first frequency signal is a signal for synchronizing a second internal operating clock, which is used to operate the display panel, with the first internal operating clock (paragraph 100, Brijesh teach sending a vertical synchronization command which is the second synchronization signal. Paragraph 67 of Brijesh shows the external clock 203 is used to generate VSYNC (second sync signal)).
In regard to claim 7, Ansari et al. teach wherein the sync request signal is generated based on at least one of a temperature, a panel leakage, a product variation information, or a driving frame rate of the display panel (elements 512, 512 and paragraphs 62-63. Ansari et al. teach upon exit of the PSR (changing the driving frame rate) the devices resynchronize).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ansari et al. in view of Brijesh further considered with Ansari et al. (US 11587531, hereafter referred to as the ‘531 patent).
In regard to claim 5, Ansari et al. and Brijesh teach all the elements of claim 5 except wherein the sync request signal is transmitted in response to a condition where communication of frame data with the display panel via the main link has not been performed for a first period of time or more.
The ‘531 patent teaches wherein the sync request signal is transmitted in response to a condition where communication of frame data with the display panel via the main link has not been performed for a first period of time or more (fig. 7, the ‘531 patent shows sending clock synchronization pings in a situation where the display has not been updated).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. and Brijesh with the clock update of the ‘531 patent. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. and Brijesh with the clock update of the ‘531 patent because the update would ensure the devices remain synched in a low power mode of operations.
Claim(s) 12, 15, 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ansari et al. in view of Brijesh further considered with Roh et al. (US 2015/0294647).
In regard to claim 12, Brijesh teaches and wherein the first frequency signal is transmitted via the side link (paragraph 36, Brijesh teaches sending control signals via the side link) but neither Ansari et al. nor Brijesh teach wherein one of a sync done signal and a sync pause signal is received via the side link.
Roh et al. teach wherein one of a sync done signal and a sync pause signal is received via the side link (paragraph 51).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. because the start and end packets would provide indication on the bounds of the transmission and would ensure accurate operations.
In regard to claim 15, Ansari et al. teach a method of operating a system on chip (SoC) (paragraph 15) comprising: generating a first internal operating clock by a clock generator and by a control circuit: generating first frame data based on the first internal operating clock (fig. 2 and paragraph 36. Ansari et al. shows outputting frame data at certain timings. This must be accomplished with a clock) but does not teach receiving, via a side link, a frame data request signal from a display panel; transmitting, via a main link, the first frame data to the display panel; receiving, via a side link, a sync request signal from the display panel; transmitting, in response to the sync request signal, a first frequency signal generated based on the first internal operating clock to the display panel.
Brijesh teaches wherein the control circuit is configured to: receiving, via a side link, a frame data request signal from a display panel (paragraph 98, sink processor transmits first sync signal to source via auxiliary link); transmitting, via a main link, the first frame data to the display panel (paragraph 99, first sync signal used as input to PLL to generate a second sync signal. Paragraph 100, transmit video data via main link), receiving, via a side link, a sync request signal from the display panel; in response to the sync request signal, transmitting, in response to the sync request signal, a first frequency signal generated based on the first internal operating clock to the display panel (paragraphs 98-100. Brijesh shows the sink device sending a sync signal to the source device via a side link. Upon reception of this signal., paragraph 100 of Brijesh shows the source device sending a vertical sync signal); wherein the side link includes a low- bandwidth communication link, and wherein the main link includes a high-bandwidth communication link (paragraph 20).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh because the synchronization signals of Brijesh would allow the device to enter PSR mode while saving power.
Roh et al. teach a sync done signal (paragraph 51).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. because the start and end packets would provide indication on the bounds of the transmission and would ensure accurate operations.
In regard to claim 19, Brijesh teaches wherein the first frequency signal is a signal for synchronizing a second internal operating clock, which is used to operate the display panel, with the first internal operating clock (paragraph 100, Brijesh teach sending a vertical synchronization command which is the second synchronization signal. Paragraph 67 of Brijesh shows the external clock 203 is used to generate VSYNC (second sync signal)).
In regard to claim 21, Ansari et al. teach a system on chip (SoC) (paragraph 15) comprising: a clock generator configured to generate a first internal operating clock; and a control circuit configured to generate and output frame data based on the first internal operating clock output from the clock generator (fig. 2 and paragraph 36. Ansari et al. shows outputting frame data at certain timings. This must be accomplished with a clock) but does not teach wherein the control circuit is configured to: receive a frame data request signal from a display panel via a side link, transmit first frame data, which is generated based on the first internal operating clock, to the display panel via a main link, receive a sync request signal from the display panel via the side link, and in response to the sync request signal, transmit a first frequency signal, which is generated based on the first internal operating clock, to the display panel.
Brijesh teaches wherein the control circuit is configured to: receive, via a side link, a frame data request signal from a display panel (paragraph 98, sink processor transmits first sync signal to source via auxiliary link), transmit, via a main link, first frame data, which is generated based on the first internal operating clock, to the display panel (paragraph 99, first sync signal used as input to PLL to generate a second sync signal. Paragraph 100, transmit video data via main link), receive, via the side link, a sync request signal from the display panel, in response to the sync request signal, transmit a first frequency signal, which is generated based on the first internal operating clock, to the display panel (paragraphs 98-100. Brijesh shows the sink device sending a sync signal to the source device via a side link. Upon reception of this signal., paragraph 100 of Brijesh shows the source device sending a vertical sync signal); wherein the side link includes a low- bandwidth communication link, and wherein the main link includes a high-bandwidth communication link (paragraph 20).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. with the synchronization signals of Brijesh because the synchronization signals of Brijesh would allow the device to enter PSR mode while saving power.
Roh et al. teach wherein one of a sync done signal and a sync pause signal is received via the side link (paragraph 51).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Ansari et al. and Brijesh with the SYNC start and end packets of Roh et al. because the start and end packets would provide indication on the bounds of the transmission and would ensure accurate operations.
Allowable Subject Matter
Claims 8-11, 13, 14, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: In regard to claims 8, 9 and 16-18, the prior art fails to teach or make obvious the sync pause signal in combination with the claim’s other features.
In regard to claim 10, the prior art fails to teach or make obvious continuing transmission of the frequency signal in response to the sync done signal.
In regard to claims 11 and 20, the prior art fails to teach or make obvious the frequency of the first frequency signal in combination with the claim’s other features.
In regard to claim 13, the prior art fails to teach or make obvious the second side link in combination with the claim’s other features.
In regard to claim 14, the prior art fails to teach or make obvious wherein the sync done and sync pause signals are received via the side link and the first frequency signal is transmitted via the main link.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621