DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The application has not been checked to the extent necessary to determine the presence of all possible typographical and grammatical errors. Applicant’s cooperation is requested in correcting any errors of which he/she may become aware in the application.
The Information Disclosure Statements filed 03/26/2025 has been considered.
Claim Objections
Claim 15 is objected to because of the following informality: Claim 15 recites on lines 5-6 the limitations “the first state” and “the second state”. There is insufficient antecedent basis for these limitations in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 10,224,949) in view of Medeiro (EP2696506A1).
Regarding claim 1, Li et al teach in figures (3) through (9) an apparatus comprising: an analog front end unit comprising a plurality of analog front end circuits (2021),…(202M, (202N) that process a detected signal; an analog-to-digital conversion unit (204) that converts an output signal of the analog front end unit to a digital code and a multiplexer (MUX 218) that outputs a processed signal by the analog front end circuits to the analog-to-digital conversion unit; wherein the analog digital conversion unit comprises: a comparator (406), a successive-approximate analog-to-digital converter (SAR ADC 204) that converts output signal of the analog front end circuit and form a digital code. Although Lee et al teach a successive approximation (SAR) ADC, they don’t specifically teach a single-slope ADC that works alongside a SAR ADC to produce separately the MSB bits (j-bits) and the LSB bits (k bits). Medeiro teaches in figure (3) an ADC system comprising a first SAR ADC (See paragraph [0033]) that outputs the MSB bits (j-bits) and a second single slope/ramp ADC ( See paragraph [0029]) that outputs the LSB bits (k bits, [paragraph 0034]). It would have been obvious to one of ordinary skill in the art, before the effective date of the claimed invention, to incorporate the teachings of Medeiro into the system of Li et al to realize a converter system having improved performance and reliability because that would reduce the amount of circuitry needed for the system (See paragraph [0010]). It is further obvious that analog-to-digital converters are widely used in medical devices such as biosensors and bio-signal detectors.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 10,224,949) in view of Medeiro (EP2696506A1) and further in view of Chae et al (US 2009/0261998).
Regarding claim 6, the combination of Li et al and Medeiro teaches the essential features of the claimed invention, as set forth above, except for the two converters sharing the comparator. However, as evidenced by Chae et al, this scheme is known in the art. Chae et al teach an analog-to-digital converter wherein two converters share a comparator (See claim 47). It would have been obvious to one of ordinary skill in the art, before the effective date of the claimed invention, to incorporate the teachings of Chae et al into the combination of Li et al and Medeiro to realize a converter system having improved performance and reliability because the use of a shared comparator would eliminate the offset effect that might result with two comparators (See paragraph [0054]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Medeiro (EP2696506A1) in view of Chae et al (US 2009/0261998).
Regarding claim 10, Medeiro teaches in figures (3) and (5) a hybrid analog-to-digital converter (the converter is a hybrid converter because it has two different sub-converters that can function independently of each other) comprising: a comparator (220); a successive-approximate analog-to-digital converter (SAR ADC, the first stage can be a SAR ADC, See [0033]) that converts an analog signal to a j bit digital code (D1); a single slope also called a single ramp ADC (See paragraph [0014]) that converts the analog signal to a k bit (D2) digital code and a register made of units (540) and (550) that saves the j bit digital code and the k bit digital code.
Medeiro does not teach that the two converters share the comparator However, as evidenced by Chae et al, this scheme is known in the art. Chae et al teach an analog-to-digital converter wherein two converters share a comparator (See claim 47). It would have been obvious to one of ordinary skill in the art, before the effective date of the claimed invention, to incorporate the teachings of Chae et al into the system of Medeiro to realize a converter system having improved performance and reliability because the use of a shared comparator would eliminate the offset effect that might result with two comparators (See paragraph [0054]).
Regarding claim 11, the combination of Medeiro and Chae et al teaches (See figure 6 of Chae et al) a sample-and hold unit (625) that samples and holds the analog signal.
Allowable Subject Matter
Claims 16-18 are allowable.
Claims 2-5, 7-9 and 12-15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH J LAUTURE whose telephone number is (571)272-1805. The examiner can normally be reached 9:30 AM-6:00 PM.
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/JOSEPH J LAUTURE/Primary Examiner, Art Unit 2845
