DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 8/10/2026.
Claims 1, 3, 5, 7, 9-11, 13-14, 16-17, and 19-20 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/10/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The Examiner thanks Applicant for amending the claims to cure the deficiencies noted in the rejections of claims 1-10, 11-16, and 17-20 under 35 U.S.C. §112(b) made in the non-final Office action dated 5/20/2026. The Examiner therefore respectfully withdraws the rejections of claims 1-10, 11-16, and 17-20 under 35 U.S.C. §112(b) made therein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-11, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2024/0272816 (“Choe”) in view of U.S. Patent No. 11,836,381 (“Esaka”).
As per claim 1, Choe substantially teaches a system (Choe, FIG. 9) comprising:
a memory device; a processing device coupled to the memory device, the processing device to perform operations comprising: (Choe, Abstract; FIG. 9, reference numerals 210 and 220; and paragraph 0100, where a storage device of the system of Choe may comprise memory controller 210 (i.e., a processor) that controls and manages non-volatile memory 220. Choe therefore substantially teaches a memory device; a processing device coupled to the memory device, the processing device to perform operations comprising);
receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of the memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. Memory controller 210 may map a Single Level Cell (SLC) area to the zone to which the data is to be written and then write the data to the SLC area mapped to the zone to which the data is to be written. The Examiner notes that an SLC by definition stores one bit per cell, which is necessarily the lowest number of bits per cell supported by non-volatile memory 220 of Choe. Choe therefore substantially teaches receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of the memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device).
Choe does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Esaka teaches memory system and methods of controlling nonvolatile memory using namespace attributes.
As per claim 1, Esaka particularly teaches:
wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a first namespace) that are associated with filesystems (e.g., a first filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a first data item) associated with the filesystem. Esaka therefore particularly teaches wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Esaka and Choe before them before the instant application was effectively filed, to modify the system of Choe to include the principles of Esaka on enabling writing data to namespaces associated with filesystems.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques to manage allocation of logical block addresses and physical block accesses within namespaces in order to minimize loss of information after system power loss (Esaka, column 3, lines 9-22).
As per claim 2, the rejection of claim 1 is incorporated, and Choe further substantially teaches:
wherein the region is designated to store data of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the region is designated to store data of a specific type).
As per claim 3, the rejection of claim 1 is incorporated, and Choe further substantially teaches:
wherein the first file system is created to store data of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. The Examiner notes that the zone to which the data is to be written may be a zone designated to store hot data, which means that the zone to which the data is to be written is a file system created for storing hot data. Choe therefore substantially teaches wherein the first file system is created to store data of a specific type).
As per claim 5, the rejection of claim 1 is incorporated, and Choe further substantially teaches wherein the operations further comprise:
receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device: (Choe, Abstract; FIG. 9; and paragraphs 0086-0096 and 0108, where the system of Choe may identify a different zone that the zone used for the first write request in order to perform a second write request that specifies data and a zone to which the data is to be written. The second zone may be a configurable zone, which may store a higher number of bits per cell relative to the zone used for the first write request. Choe therefore substantially teaches receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device).
As per claim 5, Esaka further particularly teaches:
wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a second namespace) that are associated with filesystems (e.g., a second filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a second data item) associated with the filesystem. Esaka therefore particularly teaches wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace).
As per claim 6, the rejection of claim 5 is incorporated, and Choe further substantially teaches:
wherein the second region is designated to store data not of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0086-0096 and 0108, where the system of Choe may identify a different zone that the zone used for the first write request in order to perform a second write request that specifies data and a zone to which the data is to be written. The second zone may be a configurable zone, which is not designated to store a specific type of data and may store a higher number of bits per cell relative to the zone used for the first write request. Choe therefore substantially teaches wherein the second region is designated to store data not of a specific type).
As per claim 7, the rejection of claim 5 is incorporated, and Choe further substantially teaches:
the second file system is created to store data not of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0086-0096 and 0108, where the configurable zone, which is a second file system created to store data, is not designated to store a specific type of data and may store a higher number of bits per cell relative to the zone used for the first write request. Choe therefore substantially teaches the second file system is created to store data not of a specific type).
As per claim 8, the rejection of claim 1 is incorporated, and Choe further substantially teaches:
wherein the memory device comprises a non-volatile memory device that implements Non-Volatile Memory Express (NVMe) protocol to connect to the host system via a Peripheral Component Interconnect Express (PCIe) interface: (Choe, paragraphs 0156 and 0164, where storage devices of Choe may be NVMe storage devices that connect to a host computer using a PCIe interface. Choe therefore substantially teaches wherein the memory device comprises a non-volatile memory device that implements Non-Volatile Memory Express (NVMe) protocol to connect to the host system via a Peripheral Component Interconnect Express (PCIe) interface).
As per claim 9, the rejection of claim 1 is incorporated, and Choe further substantially teaches:
wherein identifying, based on the first namespace, the region of the memory device is performed according to a mapping data structure, wherein the mapping data structure includes a plurality of records, and wherein each record of the plurality of records specifies a namespace and a corresponding region of the memory device: (Choe, Abstract; paragraph 0007; and claim 10, where the system of Choe maps logical addresses of a zone (i.e., namespace) to physical addresses of storage areas. In other words, the system of Choe uses a mapping (i.e., a mapping data structure) to map logical addresses of a zone (i.e., records specifying a namespace) to physical storage areas (i.e., corresponding regions of the memory device). Choe therefore substantially teaches wherein identifying, based on the first namespace, the region of the memory device is performed according to a mapping data structure, wherein the mapping data structure includes a plurality of records, and wherein each record of the plurality of records specifies a namespace and a corresponding region of the memory device).
As per claim 10, the rejection of claim 1 is incorporated, wherein identifying the region of the memory device further comprises:
translating a first placement identifier to a first endurance group (EG), wherein the first EG points to the region of the memory device: (Choe, paragraphs 0174-0175, where Flash Translation Layer (FTL) 2214 of Choe may manage wear leveling operations. As evidenced by the attached definition of wear leveling, which is not relied upon for any rejection but is merely and only provided as evidence, wear leveling pools flash memory blocks (i.e., groups of flash memory cells) into groups based on erase counts (i.e., endurance groups) of the flash memory blocks. Choe therefore substantially teaches translating a first placement identifier to a first endurance group (EG), wherein the first EG points to the region of the memory device).
As per claim 11, Choe substantially teaches a method (Choe, Abstract), comprising:
receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of a memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device: (Choe, Abstract; FIG. 9, reference numerals 210 and 220; and paragraphs 0100-0108, where a storage device of the system of Choe may comprise memory controller 210 (i.e., a processor) that controls and manages non-volatile memory 220. In addition, (Choe, Abstract; FIG. 9; and paragraphs 0100-0108) teaches where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. Memory controller 210 may map a Single Level Cell (SLC) area to the zone to which the data is to be written and then write the data to the SLC area mapped to the zone to which the data is to be written. The Examiner notes that an SLC by definition stores one bit per cell, which is necessarily the lowest number of bits per cell supported by non-volatile memory 220 of Choe. Choe therefore substantially teaches receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of a memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device).
Choe does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Esaka teaches memory system and methods of controlling nonvolatile memory using namespace attributes.
As per claim 11, Esaka particularly teaches:
wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a first namespace) that are associated with filesystems (e.g., a first filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a first data item) associated with the filesystem. Esaka therefore particularly teaches wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Esaka and Choe before them before the instant application was effectively filed, to modify the system of Choe to include the principles of Esaka on enabling writing data to namespaces associated with filesystems.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques to manage allocation of logical block addresses and physical block accesses within namespaces in order to minimize loss of information after system power loss (Esaka, column 3, lines 9-22).
As per claim 14, the rejection of claim 11 is incorporated, and Choe further substantially teaches further comprising:
receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device: (Choe, Abstract; FIG. 9; and paragraphs 0086-0096 and 0108, where the system of Choe may identify a different zone that the zone used for the first write request in order to perform a second write request that specifies data and a zone to which the data is to be written. The second zone may be a configurable zone, which may store a higher number of bits per cell relative to the zone used for the first write request. Choe therefore substantially teaches receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device).
As per claim 14, Esaka further particularly teaches:
wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a second namespace) that are associated with filesystems (e.g., a second filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a second data item) associated with the filesystem. Esaka therefore particularly teaches wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace).
As per claim 15, the rejection of claim 11 is incorporated, and Choe further substantially teaches:
wherein the memory device comprises a non-volatile memory device that implements Non-Volatile Memory Express (NVMe) protocol to connect to the host system via a Peripheral Component Interconnect Express (PCIe) interface: (Choe, paragraphs 0156 and 0164, where storage devices of Choe may be NVMe storage devices that connect to a host computer using a PCIe interface. Choe therefore substantially teaches wherein the memory device comprises a non-volatile memory device that implements Non-Volatile Memory Express (NVMe) protocol to connect to the host system via a Peripheral Component Interconnect Express (PCIe) interface).
As per claim 16, the rejection of claim 11 is incorporated, and Choe further substantially teaches:
wherein identifying, based on the first namespace, the region of the memory device is performed according to a mapping data structure, wherein the mapping data structure includes a plurality of records, and wherein each record of the plurality of records specifies a namespace and a corresponding region of the memory device: (Choe, Abstract; paragraph 0007; and claim 10, where the system of Choe maps logical addresses of a zone (i.e., namespace) to physical addresses of storage areas. In other words, the system of Choe uses a mapping (i.e., a mapping data structure) to map logical addresses of a zone (i.e., records specifying a namespace) to physical storage areas (i.e., corresponding regions of the memory device). Choe therefore substantially teaches wherein identifying, based on the first namespace, the region of the memory device is performed according to a mapping data structure, wherein the mapping data structure includes a plurality of records, and wherein each record of the plurality of records specifies a namespace and a corresponding region of the memory device).
As per claim 17, Choe substantially teaches a non-transitory computer readable storage medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations (Choe, Abstract; FIG. 9, reference numerals 210 and 220; and paragraph 0100) comprising:
receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of a memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. Memory controller 210 may map a Single Level Cell (SLC) area to the zone to which the data is to be written and then write the data to the SLC area mapped to the zone to which the data is to be written. The Examiner notes that an SLC by definition stores one bit per cell, which is necessarily the lowest number of bits per cell supported by non-volatile memory 220 of Choe. Choe therefore substantially teaches receiving, from a host system, a first write request, wherein the first write request includes a first data item and specifies a first namespace; identifying, based on the first namespace, a region of a memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device).
Choe does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Esaka teaches memory system and methods of controlling nonvolatile memory using namespace attributes.
As per claim 17, Esaka particularly teaches:
wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a first namespace) that are associated with filesystems (e.g., a first filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a first data item) associated with the filesystem. Esaka therefore particularly teaches wherein the first write request includes a first data item associated with a first file system, wherein the first file system is associated with a first namespace, and wherein the first write request specifies the first namespace).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Esaka and Choe before them before the instant application was effectively filed, to modify the system of Choe to include the principles of Esaka on enabling writing data to namespaces associated with filesystems.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques to manage allocation of logical block addresses and physical block accesses within namespaces in order to minimize loss of information after system power loss (Esaka, column 3, lines 9-22).
As per claim 20, the rejection of claim 17 is incorporated, and Choe further substantially teaches wherein the operations further comprise:
receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device: (Choe, Abstract; FIG. 9; and paragraphs 0086-0096 and 0108, where the system of Choe may identify a different zone that the zone used for the first write request in order to perform a second write request that specifies data and a zone to which the data is to be written. The second zone may be a configurable zone, which may store a higher number of bits per cell relative to the zone used for the first write request. Choe therefore substantially teaches receiving, from the host system, a second write request, wherein the second write request includes a second data item and a second namespace; identifying, based on the second namespace, a second region of the memory device, wherein the second region is configured to store a higher number of bits per cell than the lowest number of bits per cell in the region; and writing the second data item to the second region of the memory device).
As per claim 20, Esaka further particularly teaches:
wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace: (Esaka, Abstract; FIG. 14; and column 23, lines 4-59, where the system of Esaka comprises namespaces (e.g., a second namespace) that are associated with filesystems (e.g., a second filesystem) and are used to store data (i.e., write data) at logical addresses within the namespaces. The Examiner notes that a write request to store data within a filesystem necessarily includes data items (i.e., a second data item) associated with the filesystem. Esaka therefore particularly teaches wherein the second write request includes a second data item associated with a second file system, wherein the second file system is associated with a second namespace, and wherein the second write request specifies the second namespace).
Claims 4, 12-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2024/0272816 (“Choe”) in view of U.S. Patent No. 11,836,381 (“Esaka”) and further in view of U.S. Patent No. 9,563,566 (“Bahn”).
As per claim 4, the rejection of claim 2 is incorporated, and Choe further substantially teaches:
wherein the specific type is a hot data type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the specific type is a hot data type).
Neither Choe nor Esaka appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Bahn teaches device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage.
As per claim 4, Bahn particularly teaches:
a checkpoint data type: (Bahn, Abstract; FIG. 1, reference numeral 23; column 3, lines 29-51; and column 7, lines 53-63, where the system of Bahn maintains a journal area that stores journal data (i.e., checkpoint data). Bahn therefore particularly teaches a checkpoint data type).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Bahn, Esaka, and Choe before them before the instant application was effectively filed, to modify the combination of Esaka with Choe to include the principles of Bahn of storing journaling data in a specific area of nonvolatile memory.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques for maintaining journaling information in non-volatile memory in order to guarantee consistency during power failure followed by power reconnection and rebooting (Bahn, column 3, lines 11-14 and 48-51).
As per claim 12, the rejection of claim 11 is incorporated, and Choe further substantially teaches:
wherein the region is designated to store data of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the region is designated to store data of a specific type); and
wherein the specific type is a hot data type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the specific type is a hot data type).
Neither Choe nor Esaka appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Bahn teaches device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage.
As per claim 12, Bahn particularly teaches:
a checkpoint data type: (Bahn, Abstract; FIG. 1, reference numeral 23; column 3, lines 29-51; and column 7, lines 53-63, where the system of Bahn maintains a journal area that stores journal data (i.e., checkpoint data). Bahn therefore particularly teaches a checkpoint data type).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Bahn, Esaka, and Choe before them before the instant application was effectively filed, to modify the combination of Esaka with Choe to include the principles of Bahn of storing journaling data in a specific area of nonvolatile memory.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques for maintaining journaling information in non-volatile memory in order to guarantee consistency during power failure followed by power reconnection and rebooting (Bahn, column 3, lines 11-14 and 48-51).
As per claim 13, the rejection of claim 11 is incorporated, and Choe further substantially teaches:
wherein the first file system is created to store data of a specific type, and wherein the specific type is a hot data type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. The Examiner notes that the zone to which the data is to be written may be a zone designated to store hot data, which means that the zone to which the data is to be written is a file system created for storing hot data. In addition, (Choe, Abstract; FIG. 9; and paragraphs 0100-0108) teaches where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the first file system is created to store data of a specific type, and wherein the specific type is a hot data type).
Neither Choe nor Esaka appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Bahn teaches device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage.
As per claim 13, Bahn particularly teaches:
a checkpoint data type: (Bahn, Abstract; FIG. 1, reference numeral 23; column 3, lines 29-51; and column 7, lines 53-63, where the system of Bahn maintains a journal area that stores journal data (i.e., checkpoint data). Bahn therefore particularly teaches a checkpoint data type).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Bahn, Esaka, and Choe before them before the instant application was effectively filed, to modify the combination of Esaka with Choe to include the principles of Bahn of storing journaling data in a specific area of nonvolatile memory.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques for maintaining journaling information in non-volatile memory in order to guarantee consistency during power failure followed by power reconnection and rebooting (Bahn, column 3, lines 11-14 and 48-51).
As per claim 18, the rejection of claim 17 is incorporated, and Choe further substantially teaches:
wherein the region is designated to store data of a specific type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the region is designated to store data of a specific type); and
wherein the specific type is a hot data type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the specific type is a hot data type).
Neither Choe nor Esaka appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Bahn teaches device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage.
As per claim 18, Bahn particularly teaches:
a checkpoint data type: (Bahn, Abstract; FIG. 1, reference numeral 23; column 3, lines 29-51; and column 7, lines 53-63, where the system of Bahn maintains a journal area that stores journal data (i.e., checkpoint data). Bahn therefore particularly teaches a checkpoint data type).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Bahn, Esaka, and Choe before them before the instant application was effectively filed, to modify the combination of Esaka with Choe to include the principles of Bahn of storing journaling data in a specific area of nonvolatile memory.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques for maintaining journaling information in non-volatile memory in order to guarantee consistency during power failure followed by power reconnection and rebooting (Bahn, column 3, lines 11-14 and 48-51).
As per claim 19, the rejection of claim 17 is incorporated, and Choe further substantially teaches:
wherein the first file system is created to store data of a specific type, and wherein the specific type is a hot data type: (Choe, Abstract; FIG. 9; and paragraphs 0100-0108, where a write request received from a host includes data and a zone (i.e., a namespace) to which the data is to be written. The Examiner notes that the zone to which the data is to be written may be a zone designated to store hot data, which means that the zone to which the data is to be written is a file system created for storing hot data. In addition, (Choe, Abstract; FIG. 9; and paragraphs 0100-0108) teaches where the SLC area may be designated to store hot data, which is data of a specific type. Choe therefore substantially teaches wherein the first file system is created to store data of a specific type, and wherein the specific type is a hot data type).
Neither Choe nor Esaka appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Bahn teaches device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage.
As per claim 19, Bahn particularly teaches:
a checkpoint data type: (Bahn, Abstract; FIG. 1, reference numeral 23; column 3, lines 29-51; and column 7, lines 53-63, where the system of Bahn maintains a journal area that stores journal data (i.e., checkpoint data). Bahn therefore particularly teaches a checkpoint data type).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Bahn, Esaka, and Choe before them before the instant application was effectively filed, to modify the combination of Esaka with Choe to include the principles of Bahn of storing journaling data in a specific area of nonvolatile memory.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing techniques for maintaining journaling information in non-volatile memory in order to guarantee consistency during power failure followed by power reconnection and rebooting (Bahn, column 3, lines 11-14 and 48-51).
Response to Arguments
In the Remarks dated 8/10/2026, Applicant substantially argues:
Neither Choe nor Bahn alone or in combination teaches each and every feature of the amended claims.
Applicant’s arguments dated 8/10/2026 have been fully considered, but they are not persuasive. The Examiner notes that the new Esaka reference in combination with the prior art of record clearly teaches the limitations added via amendment. The Examiner further notes that the new grounds of rejection were necessitated by Applicant’s amendments to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
