DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 7-12 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 7-12 of copending Application No. 19/061,391 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Note that the integrator circuit in claim 7 of the instant application inherently includes a path for a signal to pass through the integrator circuit. Also, the delay locked loop in claim 7 of the instant application inherently includes a delay element.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 12 of copending Application No. 19/061,391 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-6 and 13 of the instant application are merely broad presentations of claims 1-6 and 12 of copending Application No. 19/061,361 with the exception of the MEMS device in claim 13 of the instant application.
However, it is well-known to those of ordinary skill in the art to utilize a MEMS device as a high-Q resonator device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to embody the claimed high-Q resonator of the copending application as a high-Q MEMS resonator because such a modification would have been a replacement with a well-known high-Q resonator device.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-5 and 7-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The claims recite the following limitations having insufficient antecedent basis:
Claim 2, line 1: “the LRC input signal”;
Claim 3, line 1: “the sensor”;
Claim 4, line 4: “the signal divider circuitry”;
Claim 5, line 1: “the limiter”;
Claim 5, line 2: “the signal divider”;
Claim 7, line 5: “the reference signal”;
Claim 7, line 6: “the reference signal frequency”;
Claim 11, line 1: “the integrator circuit path”;
Claim 11, line 2: “the calibrated reference signal”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2009/0256601; “Zhang”).
Regarding claim 1, Zhang teaches a circuit (figure 2) for controlling the output of a frequency resonator (XO), the circuit comprising:
a time-to-digital convertor (TDC) loop (loop through TDC 231) configured to be locked to a reference signal (of XO); and
a lock range control (LRC) circuit (260-264) coupled to the TDC loop (at divider 270) and configured to provide a signal (from 264) to the TDC loop, wherein the signal (from 264) is configured to adjust an output signal (Vrf) of the TDC loop.
As for claim 5, Zhang teaches wherein a limiter (264) is configured to operate at a frequency range such that an output of the limiter is within an acceptable input range of a signal divider circuitry (270).
Claims 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwasniewski et al. (US 7,675,332; “Kwasniewski”).
Regarding claim 7, Kwasniewski teaches a circuit (figure 4) for adjusting signal frequency based upon changes in operational parameters, the circuit comprising:
an integrator circuit (410, 420, 431, 432) configured to generate an output signal (OUT) having an output frequency (inherent property of periodic signal); and
a delay locked loop (400) configured to offset a phase of a reference signal (CLK) based upon an initial calibration (with Vtf) such that the reference signal (CLK) frequency matches (according to similar delays 111-115 and 421-424; col. 6, lines 32-40 and 50-53) the output frequency of the output signal (OUT).
As for claim 8, Kwasniewski teaches wherein the integrator circuit (410, 420, 431, 432) comprises a buffering amplifier (410) and a filter (432) configured to remove harmonics from the reference signal (CLK).
Claims 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenyon et al. (US 2020/0336288; “Kenyon”).
Regarding claim 7, Kenyon teaches a circuit (figure 2) for adjusting signal frequency based upon changes in operational parameters, the circuit comprising:
an integrator circuit (111RX, 230; Kenyon uses integrators for lowpass filters, such as LPF 237; para. [0027]) configured to generate an output signal (from 232) having an output frequency; and
a delay locked loop (221-223) configured to offset a phase of a reference signal (input to 111RX) based upon an initial calibration (with control signal 224) such that the reference signal frequency matches (using phase detector 225) the output frequency of the output signal (from 232).
As for claim 8, Kenyon wherein the integrator circuit (111RX, 230) comprises a buffering amplifier (111RX) and a filter (237) configured to remove harmonics from the reference signal (input to 111RX).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cioffi et al. (US 7,449,968; “Cioffi”).
Regarding claims 2 and 3, Zhang teaches the circuit of claim 1, as detailed above, but fails to teach wherein the LRC circuit comprises a temperature sensor generating a temperature-dependent signal.
However, it is well-known to those of ordinary skill in the art to embody a PLL frequency divider control circuit with a delta-sigma modulator receiving a temperature-dependent signal from a temperature sensor. For example, see figure 3 of Cioffi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a temperature sensor to the frequency divider control circuit (260-264) of Zhang because such a modification would have provided the well-known benefit of temperature compensation for the frequency divider.
As for claim 4, Zhang modified by Cioffi teaches an analog to digital converter (338 of Cioffi) to convert an output of the temperature sensor (306) to a digital signal for processing by signal divider circuitry (324 in Cioffi; 270 in Zhang)
Zhang modified by Cioffi fails to teach a conditioning circuit to filter the output of the temperature sensor.
However, it is well-known to those of ordinary skill in the art to filter DC control signals to eliminate noise in the control signals.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a conditioning circuit to filter the output of the temperature sensor of Zhang/Cioffi because such a modification would have provided the well-known benefit of eliminating noise in the temperature-dependent signal.
Regarding claim 6, Zhang teaches the circuit of claim 1, as detailed above, but fails to teach wherein the circuit comprises a high-Q circuit configured to resonate at a specific frequency with minimal energy loss over time.
However, it is well-known to those of ordinary skill in the art to embody a PLL reference resonator with a high-Q MEMS reference resonator. For example, see col. 4, lines 39-41 of Cioffi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a high-Q MEMS resonator as the reference resonator of Zhang because such a modification would have been a replacement with a well-known PLL reference resonator device.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwasniewski in view of Stubbs et al. (US 2002/0089361; "Stubbs").
Regarding claims 9 and 10, Kwasniewski teaches wherein the delay locked loop (400) comprises a delay element (111-115), but fails to teach wherein the integrator circuit is further configured to adjust signal frequency based upon changes in operational temperature; and wherein the delay element is configured to offset the phase of the reference signal based upon an initial temperature-based circuit calibration.
However, it is well-known to those of ordinary skill in the art to compensate for frequency/phase variations from temperature fluctuations with a delay locked loop. For example, see para. [0014] of Stubbs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the DLL of Kwasniewski with temperature compensation because such a modification would have provided the well-known benefit of frequency/phase correction from temperature variations.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kwasniewski in view of Seeger et al. (US 2010/0253437; "Seeger").
Regarding claims 12 and 13, Kwasniewski teaches the circuit of claim 7, as detailed above, but fails to teach wherein the integrator circuit comprises a high-Q MEMS device configured to resonate at a specific frequency with minimal energy loss over time.
However, it is well-known to those of ordinary skill in the art to embody a DLL reference resonator with a high-Q MEMS reference resonator. For example, see para. [0007] of Seeger.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a high-Q MEMS resonator as the reference resonator of Kwasniewski because such a modification would have been a replacement with a well-known DLL reference resonator device.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon in view of Cioffi.
Regarding claims 9 and 10, Kenyon teaches wherein the delay locked loop (221-223) comprises a delay element (221), but fails to teach wherein the integrator circuit is further configured to adjust signal frequency based upon changes in operational temperature; and wherein the delay element is configured to offset the phase of the reference signal based upon an initial temperature-based circuit calibration.
However, it is well-known to those of ordinary skill in the art to compensate for frequency/phase variations from temperature fluctuations in a PLL. For example, see figure 3 of Cioffi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the PLL of Kenyon with temperature compensation because such a modification would have provided the well-known benefit of frequency/phase correction from temperature variations.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon in view of Seeger.
Regarding claims 12 and 13, Kenyon teaches the circuit of claim 7, as detailed above, but fails to teach wherein the integrator circuit comprises a high-Q MEMS device configured to resonate at a specific frequency with minimal energy loss over time.
However, it is well-known to those of ordinary skill in the art to embody a PLL reference resonator with a high-Q MEMS reference resonator. For example, see para. [0007] of Seeger.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a high-Q MEMS resonator as the reference resonator of Kenyon because such a modification would have been a replacement with a well-known PLL reference resonator device.
Conclusion
The prior art references made of record and not relied upon teach circuits, comprising: TDC loops, LRC circuits, temperature sensors, controlled frequency dividers, integrator circuits, and DLLs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEVI GANNON/Primary Examiner, Art Unit 2836 June 10, 2026
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