DETAILED ACTION
1. Claims 1-20 are pending in this examination.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4.1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4.2. Claims 1-6, 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11416332 issued to Eckhardt et al (“Eckhardt”) in view of US Patent Application No. 20120011352 to Shimatani et al (“Shimatani”).
As per claim 1, Eckhardt discloses a method for protecting a microcontroller comprising (col. 3, lines 37-50, protect an Ethernet PHY against undetected data corruption in the PHY registers. Table 100 shows a PHY register block having columns 110, 120, 130 and 140. Column 110 shows the name and/or address of each of the registers in the PHY. Column 120 represents the PHY registers selected to be protected using a register lock. Column 130 represents the PHY registers selected to be protected using a checksum. Column 140 represents the PHY registers selected to be protected using a parity bit or error correction code (ECC).
calculating a first checksum on a content of at least one configuration register of the microcontroller stored in a first memory; storing, into the first memory, of the first checksum (col. 5, lines 17-36, The contents of the PHY configuration registers are determined by design and characterization prior to compiling the code that will be loaded into the microcontroller. Once the contents of the PHY configuration registers are determined, the data is loaded into the checksum generator 244 as a PHY register image 240. The checksum generator 244 calculates a checksum 250 of the PHY register image 240 using a suitable checksum algorithm such as e.g. cyclic redundancy check (CRC), fig. 2 and associated texts, Register image 240 is loaded (not shown) into memory 212 of the microcontroller 210 prior to system initialization. The microcontroller 210 could also be a digital signal processor, microprocessor, or a system-on-a-chip. The checksum 250 is also loaded into the microcontroller 210 prior to system initialization. The PHY device 230 is coupled to the microcontroller 210 by an MDIO interface
220. The microcontroller 210 loads the PHY register image into the PHY registers 232 during system initialization via the serial MDIO Interface 220
following startup. The checksum 250 is also loaded at startup from the microcontroller 210 to the dedicated checksum register 238 in the PHY device 230 as part of the initialization process); and
copying the first checksum and the content of the at least one configuration register to a second memory (col. 5, lines 20-35, Register image 240 is loaded (not shown) into memory 212 of the microcontroller 210 prior to system initialization… the checksum 250 is also loaded into the microcontroller 210 prior to system initialization.; col.6, lines 15-25, checksum register 350 (storing);
- in a boot phase (col. 30-35, The microcontroller 210 loads the PHY register image into the PHY registers 232 during system initialization, col., 8, lines 3-10)
copying of the first checksum and of the content of the at least one configuration register from the second memory to the first memory (col. 5, lines 25-40, The microcontroller 210 loads the PHY register image into the PHY registers 232
during system initialization via the serial MDIO Interface 220 following startup. The checksum 250 is also loaded at startup from the microcontroller 210 to the dedicated checksum register 238 in the PHY device 230 as part of the initialization process.
comparing a second checksum, calculated on the content of the at least one configuration register copied from the second memory, and the first checksum copied from the second memory (col. 5, lines 46-54, A checksum checker 234 is coupled to the register set 232. During runtime, the checksum checker 234 can verify the PHY register contents by reading the selected registers or the complete register set 232, calculating a current value of the checksum for those registers, and comparing the current checksum to the saved checksum in the checksum register 238 col. 8, lines 9-24, At 530, the checksum generator reads the contents of the registers and generates an initial checksum, which is stored in the checksum register at 540. At step 550, a checksum trigger source communicates to the checksum generator 360 that the checksum generator needs to read the current contents of the PHY registers 332 and generate a current checksum at step 560. The checksum checker 334 receives the current checksum from the checksum generator and the initial checksum from the checksum register 338 at step 570. If the values of the initial checksum and the current checksum are equal at 580, the process loops back to step 550 and waits for a trigger source to generate the next trigger. If the values of the initial checksum and the current checksum are not equal at 580, the PHY reports the error to the microcontroller, and the microcontroller takes the appropriate corrective action, such as reloading the register image to the register set).
Furthermore, Eckhardt discloses the calculation of first checksum is performe during a compile time or design time (col. 5, lines 17-36), but does not explicitly disclose however in the same field of endeavor, Shimatani discloses in a personalization phase ([0040]-[0041], starting an information processing apparatus includes a plurality of processing units each having a hashing unit that performs a hash operation, a startup control unit that controls startup of the information processing apparatus, and a hardware resource, the method including: determining whether to detect configuration modification of the information processing apparatus upon startup of the information processing apparatus also see [0012]-[0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Eckhardt with the teaching of Shimatani by including the feature of startup, in order for Eckhardt’s system to improving the security level, When a match of a pair of a first configuration register value obtained by a configuration register value obtainment unit and a first configuration register value related to the first configuration register value stored in a storage unit with being related to the first startup control unit, or a match of a pair of a second configuration register value obtained by the configuration register value obtainment unit and a second configuration register value related to the second configuration register value stored in the storage unit with being related to the second startup control unit, is detected, startup processing of an information processing apparatus is continued. Thereby, the startup processing can be completed even when a part of processing units is swapped with a spare processing unit having the same configuration, and the functions of the startup control units can be effectively exploited (Shimatani, abstract).
As per claim 2, the combination of Eckhardt and Shimatani discloses the method of claim 1, wherein, when the first checksum and the second checksum are different in the comparison, then one or more values of the content of the configuration register copied from the second memory are modified (Eckhardt, col. 1, 25-60).
As per claim 3, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein, when the first checksum and the second checksum are identical in the comparison, then the content of the configuration register copied is not modified (Eckhardt, col. 8, 20-25). (Shimatani, [0092]). The motivation regarding the obviousness of claim 1is also applied to claim 3.
As per claim 4, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein a configuration of the microcontroller, defined by the one or more values modified of the content of the configuration register, corresponds to a maximum level of access restriction.
As per claim 5, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein a configuration of the microcontroller, defined by the one or more values modified of the content of the configuration register, corresponds to a maximum level of addressing mode restriction (Shimatani, [0092]). The motivation regarding the obviousness of claim 1is also applied to claim 5.
As per claim 6, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein a configuration of the microcontroller, defined by the one or more values modified of the content of the configuration register, corresponds to a maximum level of boot program access prohibition (Shimatani, [0092]). The motivation regarding the obviousness of claim 1is also applied to claim 6.
As per claim 8, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein a configuration of the microcontroller, defined by the one or more values modified of the content of the configuration register, comprises a microcontroller life cycle state corresponding to a mode where one or more content of one or more programs of the microcontroller are inaccessible (Shimatani, [0092]). The motivation regarding the obviousness of claim 1is also applied to claim 8.
As per claim 9, the combination of Eckhardt and Shimatani discloses the e method of claim 1, wherein the second checksum is calculated periodically (Eckhardt, col. 6, 65-76, col. 3, lines 25-30).
As per claim 10, the combination of Eckhardt and Shimatani discloses the method of claim 1, wherein the copying of the first checksum is performed in a register of the first memory (Eckhardt, col. 5, lines 33-38, fig. 2 and associated texts).
As per claim 11, the combination of Eckhardt and Shimatani discloses the method of claim 1, wherein the first memory is a volatile memory (Shimatani, [0077]). The motivation regarding the obviousness of claim 1is also applied to claim 11.
As per claim 12, the combination of Eckhardt and Shimatani discloses the e method of claim 1, wherein the second memory is a non- volatile memory (Shimatani, [0079]). The motivation regarding the obviousness of claim 1is also applied to claim 12.
As per claim 13, the combination of Eckhardt and Shimatani discloses the method of claim 1, wherein the first checksum and the second checksum are based on cyclic redundancy calculations (Eckhardt, col. 5, lines 17-25, col. 6, lines 10-20).
As per claim 14, the combination of Eckhardt and Shimatani discloses the method of claim 2, wherein calculating the first checksum and the second checksum as well as comparing the first checksum and the second checksum are implemented by a memory interface of the first memory or of the second memory (Eckhardt, col. 5, lines 31-38, fig. 2 and associated texts).
As per claim 15, the combination of Eckhardt and Shimatani discloses the method of claim 1, wherein the first memory and the second memory are memories of the microcontroller Eckhardt, col. 5, lines 25-67).
Claim 16, is rejected for similar reasons as stated above, and claim 1.
Claim 17, is rejected for similar reasons as stated above, and claim 2.
Claim 18, is rejected for similar reasons as stated above, and claim 3.
Claim 19, is rejected for similar reasons as stated above, and claim 4.
Claim 20, is rejected for similar reasons as stated above, and claim 5.
4.3. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Eckhardt and Shimatani as applied to claim above, and in view of US Patent Application No. 20180373598 to Mondello et al (“Mondello”).
As per claim 7, the combination of Eckhardt and Shimatani discloses the invention as described above. Eckhardt and Shimatani do not explicitly disclose however, In the same field of endeavor, Mondello discloses the method of claim 6, wherein one or more levels of boot program access prohibition correspond, to levels of protection of successively-installed boot programs, the levels of protection being implemented by using a monotonic counter ([0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Eckhardt with the teaching of Mondello/Shimatani by including the feature of startup, in order for Eckhardt’s system to providing the memory device with dedicated security hardware increases the speed and performance of the computer system, as hardware implementation of cryptographic functions can be one or more orders of magnitude (e.g., 10 to 100 times) faster than software implementation thereof. Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord (Mondello, abstract).
5.1. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure as the prior art discloses many of the claim features (See PTO-form 892).
5.2. a). US Patent Application No. 20120160922 to Cu et al., discloses a method implemented by an electronic entity including a nonvolatile rewritable memory and a read-only memory, the method comprising: reception of at least one write command for writing to the nonvolatile memory, and en response to the command, writing configuration data to the nonvolatile memory, wherein the configuration data are obtained based on so-called prerecorded data read in the read-only memory
b). US Patent Application No. 20140164647 to Lee et al., discloses a process to manage data between one or more MDIO manageable devices situated on the same bus utilizing the MDIO protocol. The data management efficiency can be increased through the use of an MDIO protocol that includes a checksum mode. The MDIO protocol including the checksum mode can provide write confirmations while reducing the overhead for confirmed write operations by omitting read-back and compare sequences following write transactions
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARUNUR RASHID whose telephone number is (571)270-7195. The examiner can normally be reached 9 AM to 5PM.
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HARUNUR . RASHID
Primary Examiner
Art Unit 2497
/HARUNUR RASHID/Primary Examiner, Art Unit 2497
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