DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Missing patent number U.S. 12,321,609 in the related allocation(s) section.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21, 23, 25-29, 31-34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12of U.S. Patent No. 12,321,609. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following analysis:
Instant application 19/091,566.
Patent 12,321,609.
21. An electronic apparatus, comprising: one or more substrates; and circuitry coupled to the one or more substrates, the circuitry to: track transactions that access a memory level of memory, control access to at least the memory level of the memory, control a roll back of at least the memory level of the memory based on the tracked transactions, track an order and time of writes that are inserted in the memory level, and update a state of insertions in a lookup table based on the tracked order and time, in response to a request to roll back the memory level.
1.An electronic apparatus, comprising: one or more substrates; and circuitry coupled to the one or more substrates, the circuitry to: track transactions that access a first memory level of a multi-level memory, control access to at least the first memory level of the multi-level memory, control a roll back of at least the first memory level of the multi-level memory based on the tracked transaction, track an order and time of writes that are inserted in the first memory level, and update a state of insertions in a lookup table based on the tracked order and time, in response to a request to roll back the first memory level.
23. The apparatus of claim 21, wherein the circuitry is further to: maintain a queue of time information for writes inserted in the memory level.
2. The apparatus of claim 1, wherein the circuitry is further to maintain a queue of time information for writes inserted in the first memory level.
25. An electronic apparatus, comprising: one or more substrates; and circuitry coupled to the one or more substrates, the circuitry to: control a roll back of memory in response to a request to roll back the memory; determine respective numbers of sectors to roll back for each memory level of the memory in response to the request to roll back the memory; and issue respective rollback commands that indicate the respective determined numbers of sectors to rollback each memory level of the memory.
4. An electronic apparatus, comprising: one or more substrates; and circuitry coupled to the one or more substrates, the circuitry to: control a roll back of a multi-level memory in response to a request to roll back the multi-level memory; determine respective numbers of sectors to roll back for each level of the multi-level memory in response to the request to roll back the multi-level memory; and issue respective rollback commands that indicate the respective determined numbers of sectors to rollback each level of the multi-level memory.
26. The apparatus of claim 25, wherein the circuitry is further to: determine a first number of sectors to roll back a first memory level of the memory; and determine a second number of sectors to roll back a second memory level of the memory based on a number of sectors indicated in the request to roll back the memory reduced by the determined first number of sectors.
5. The apparatus of claim 4, wherein the circuitry is further to: determine a first number of sectors to roll back a first memory level of the multi-level memory; and determine a second number of sectors to roll back a second memory level of the multi-level memory based on a number of sectors indicated in the request to roll back the multi-level memory reduced by the determined first number of sectors.
27. The apparatus of claim 25, wherein the circuitry is further to: determine an amount of time for rollback of each memory level of the memory in response to a request to roll back the memory.
6. The apparatus of claim 4, wherein the circuitry is further to: determine an amount of time for rollback of each level of the multi-level memory in response to a request to roll back the multi-level memory.
28. The apparatus of claim 27, wherein the circuitry is further to: issue respective roll back commands that indicate the amount of time to roll back each memory level of the memory.
7. The apparatus of claim 6, wherein the circuitry is further to: issue respective roll back commands that indicate the amount of time to roll back each level of the multi-level memory.
29. An electronic system, comprising: a memory that includes at least a front-end media device and a back-end media device; first circuitry communicatively coupled to the memory, the first circuitry to: track transactions that access the memory; control access to at least the front-end media device; track an order and time of writes that are inserted in the front-end media device; and update a state of insertions in a lookup table based on the tracked order and time, in response to a request to roll back the front-end media device; and second circuitry communicatively coupled to the first circuitry to control a roll back of the memory.
8. An electronic system, comprising: a multi-level memory that includes at least a front-end media device and a back-end media device; first circuitry communicatively coupled to the multi-level memory, the first circuitry to: track transactions that access the multi-level memory; control access to at least the front-end media device; track an order and time of writes that are inserted in the front-end media device; and update a state of insertions in a lookup table based on the tracked order and time, in response to a request to roll back the front-end media device; and second circuitry communicatively coupled to the first circuitry to control a roll back of the multi-level memory.
31. The system of claim 29, wherein the second circuitry is further to: determine a first number of sectors to rollback for the front-end media device in response to a request to roll back the memory; and determine a second number of sectors to rollback for the back-end media device in response to the request to roll back the memory.
9. The system of claim 8, wherein the second circuitry is further to: determine a first number of sectors to rollback for the front-end media device in response to a request to roll back the multi-level memory; and determine a second number of sectors to rollback for the back-end media device in response to the request to roll back the multi-level memory.
32. The system of claim 31, wherein the second circuitry is further to: issue a first rollback command to the first circuitry that indicates the first number of sectors to roll back the front-end media device; and issue a second rollback command to the first circuitry that indicates the second number of sectors to roll back the back-end media device.
10. The system of claim 9, wherein the second circuitry is further to: issue a first rollback command to the first circuitry that indicates the first number of sectors to roll back the front-end media device; and issue a second rollback command to the first circuitry that indicates the second number of sectors to roll back the back-end media device.
33. The system of claim 29, wherein the second circuitry is further to: determine an amount of time for rollback of memory each level of the memory in response to a request to roll back the memory.
11. The system of claim 8, wherein the second circuitry is further to: determine an amount of time for rollback of each level of the multi-level memory in response to a request to roll back the multi-level memory.
34. The system of claim 33, wherein the second circuitry is further to: issue respective roll back commands to the first circuitry for each memory level of the memory that indicate the amount of time to roll back each level of the memory.
12. The system of claim 11, wherein the second circuitry is further to: issue respective roll back commands to the first circuitry for each level of the multi-level memory that indicate the amount of time to roll back each level of the multi-level memory.
Conclusion
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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