Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-2, 8, 10-11, 17, and 19-23 have been amended. No claims have been cancelled or added. Claims 1-23 are currently under review.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 12, 2025 and September 24, 2025 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 10, 19, and 23 (and their dependents claims 2-18, and 20-22) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to Claim 1 and its dependents claims 2-22, the claims indicate “a configuration solution of a driver chip” and that “the configuration solution comprises a first configuration solution and a second configuration solution”. The definition of configuration is an arrangement of elements in a particular form or combination. It is unclear if the claims are directed to having to different separate physical components or whether the claims are directed to how the components are utilized to generate two different solutions. For the purposes of examination, the Office will interpret a first configuration as a first mode and a second configuration as a second mode.
With respect to Claim 10, line 19 indicates “and the second direct circuit” however claim 10 only mentions “second direct path” and “second voltage regulation circuit”, therefore it is unclear whether the Applicant intended for the claims to indicate “second direct path” or “second voltage regulation circuit”. For the purposes of examination, the Office will interpret the claims “and the second direct circuit” as “and the second direct path”.
With respect to Claim 19, the claims indicate “wherein in the second configuration solution, the driver chip is configured to be used in a high-voltage display device” however claim 1 from which it depends indicates “in the first configuration solution, the driver chip is configured to be used in a low-voltage display device”, therefore it is not possible for the display device to be both a low-voltage display device and a high-voltage display device.
With respect to Claim 23, the claims indicate “a display device, comprising a driver chip, wherein the driver chip is configured by using a configuration solution, wherein the display device is a low-voltage display device or a high-voltage display device … the configuration solution comprises a first configuration solution and a second configuration solution”. The definition of configuration is an arrangement of elements in a particular form or combination. It is unclear if the claims are directed to having to different separate physical components or whether the claims are directed to how the components are utilized to generate two different solutions. It is not possible for the display device to be both a low-voltage display device and a high-voltage display device, therefore the claims are indefinite. For the purposes of examination, the Office will interpret a first configuration as a first mode and a second configuration as a second mode.
Claim Objections
Claim 1 is objected to because of the following informalities: typographic errors. Appropriate correction is required.
Claim 1, line 9: “in the first configuration solution, the driver chip is configured to be used in the display device that is a low-voltage display device”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 19-20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al. (Pub. No.: US 2018/0053463 A1) hereinafter referred to as Kong in view of Kuo et al. (Pub. No.: US 2016/0171951 A1) hereinafter referred to as Kuo.
With respect to Claim 1, Kong teaches a configuration solution of a driver chip (fig. 1, item 1100; ¶29) in a display device (fig. 1, item 1000; fig. 15, item 6000; ¶26; ¶29), wherein: the driver chip comprises a first voltage boost circuit (fig. 1, item 1120/fig. 2/11, item 1122/4122; ¶33; ¶35) and a first voltage regulation circuit (fig. 1, item 1130; ¶33; ¶36) that are coupled, the first voltage boost circuit is configured to boost a received voltage and then transmit the boosted voltage to the first voltage regulation circuit (¶35), and the first voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage (¶36; ¶156); the configuration solution comprises a first configuration solution and a second configuration solution (¶31, first configuration: low-power mode, second configuration: normal mode); in the first configuration solution, the driver chip is configured to be used in a low-voltage display device (¶3, wearable devices that include a display device; ¶31-32, the display device is a low-voltage display device when in a low-power mode); the low-voltage display device comprises: a first gate driving circuit (fig. 15, item 6400; ¶123), a first display screen (fig. 15, item 6300; ¶123), and a first direct path (fig. 2/11, path connecting item VS1 to item 1131/4131); the low-voltage display device comprises a first high voltage power supply input end, a first medium-voltage power supply input end, and a first low voltage power supply input end (¶34, “The switching circuit 1110 may select at least one of power supply voltages VS1 and VS2 received from the outside, and the selected power supply voltage may be supplied to the boosting circuit 1120 … For brevity of description and illustration, only two power supply voltages VS1 and VS2 are illustrated in FIG. 1, but three or more power supply voltages may be supplied to the switching circuit 1110, and the inventive concepts are not limited thereto”); the first voltage regulation circuit is coupled to the first high voltage power supply input end through the first direct path (fig. 2/11, item 1131/4131 & 4132 is connected to VS1; ¶80, “the first power supply voltage VS1 is higher in level than the second power supply voltage VS2”); the first gate driving circuit is configured to provide a gate driving signal for a pixel driving circuit in the first display screen (¶138); and a first positive power supply voltage of the first gate driving circuit is less than a first high voltage power supply voltage of the first high-voltage power supply input end (¶10, in a first mode… an absolute value of the external voltage being greater than an absolute value of the first output voltage. In a second mode… an absolute value of the second output voltage being less than an absolute value of the first voltage and less than an absolute value of the external voltage); the first high-voltage power supply input end, the first medium-voltage power supply input end, the first low-voltage power supply input end, and a first control end are all coupled to the first voltage boost circuit (fig. 2/fig. 11; ¶34); and the first control end is configured to receive a first control signal to turn on and turn off the first voltage boost circuit (fig. 2/11, CTRL1/ENB1 and CTL2/ENB2; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2); and the first voltage regulation circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end through the first direct path (fig. 2/11, VS1 is directly connected to item 1131/4131), regulate the first high-voltage power supply voltage, and then generate and output the first positive power supply voltage to the first gate driving circuit (fig. 5; ¶65, “The first power supply voltage VS1 may be applied to a first, or source terminal of the pass transistor PT, and the output voltage VO1/VO2 may be output through a second, or drain terminal of the pass transistor PT”).
Kong does not mention that the low-voltage display device comprises a first circuit board, such that the first circuit board comprises a first high voltage power supply input end, a first medium-voltage power supply input end, and a first low voltage power supply input end.
Kuo teaches a driver chip (fig. 3; ¶21) in a display device, wherein the driver chip comprises a charge pump circuit (fig. 3, item 60; ¶21); the display device comprises a first circuit board (fig. 3, item 2), a first gate driving circuit (fig. 3, items 22 and 24; ¶21), and a first display screen (fig. 3, item 1); the first circuit board comprises: a first high-voltage power supply input end (fig. 3, item VSP), a first medium-voltage power supply input end (fig. 3, item VCC), and a first low-voltage power supply input end (fig. 3, item VSN).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the configuration solution of a driver chip in a display device of Kong, such that the low-voltage display device comprises a first circuit board, resulting in the first circuit board comprises a first high voltage power supply input end, a first medium-voltage power supply input end, and a first low voltage power supply input end, as taught by Kuo so as to provide an implementation method of the components.
With respect to Claim 2, claim 1 is incorporated, Kong teaches wherein in a process in which the driver chip performs the first configuration solution, the first control end is configured to receive the first control signal to turn off the first voltage boost circuit (fig. 2/11, CTRL1/ENB1 and CTL2/ENB2; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2).
With respect to Claim 3, claim 1 is incorporated, Kong teaches wherein the driver chip comprises a first register (fig. 11, item 4150; ¶95), and the first register is configured to transmit the first control signal to the first control end (fig. 11, item 4150 is a register since a first control signal is transmitted to the first voltage boost circuit).
With respect to Claim 4, claim 1 is incorporated, Kong teaches wherein the first direct path comprises a first resistor (fig. 2/11, the first direct path from item VS1 to the voltage regulator has a line resistance and also acts a first resistor).
With respect to Claim 5, claim 4 is incorporated, Kong teaches wherein the first resistor comprises a 0-ohm resistor (fig. 2/11, the first direct path from item VS1 to the voltage regulator has a line resistance and also acts a first resistor, in this case it is 0 ohm).
With respect to Claim 6, claim 1 is incorporated, Kong teaches wherein the first direct path comprises a first signal line (fig. 2/11).
With respect to Claim 7, claim 1 is incorporated, Kong teaches wherein the first direct path is integrated into the driver chip (fig. 2/11; ¶45; ¶95).
With respect to Claim 19, claim 1 is incorporated, Kong teaches wherein in the second configuration solution, the driver chip is configured to be used in a high-voltage display device (¶3, plasma display PDP; ¶31; ¶35, the display device is a high-voltage display device when in a normal mode); the high-voltage display device comprises a second gate driving circuit (fig. 15, item 6400; ¶123), and a second display screen (fig. 15, item 6300; ¶123); the high-voltage display device comprises a second high-voltage power supply input end, a second medium-voltage power supply input end, and a second low voltage power supply input end (¶34, “The switching circuit 1110 may select at least one of power supply voltages VS1 and VS2 received from the outside, and the selected power supply voltage may be supplied to the boosting circuit 1120 … For brevity of description and illustration, only two power supply voltages VS1 and VS2 are illustrated in FIG. 1, but three or more power supply voltages may be supplied to the switching circuit 1110, and the inventive concepts are not limited thereto” – when used in a high-voltage display device VS1 is a second high-voltage power supply, VS2 is a second medium-voltage power supply, and VS3 is a second low-voltage power supply); the second gate driving circuit is configured to provide a gate driving signal for a pixel driving circuit in the second display screen (¶138); and a second positive power supply voltage of the second gate driving circuit is greater than a second high-voltage power supply voltage of the second high-voltage power supply input end (¶10, in a first mode… an absolute value of the external voltage being greater than an absolute value of the first output voltage. In a second mode… an absolute value of the second output voltage being less than an absolute value of the first voltage and less than an absolute value of the external voltage); wherein the first voltage boost circuit (fig. 11, item 4121) is configured to receive the second high-voltage power supply voltage of the second high-voltage power supply input end and at least one of a voltage of the second medium-voltage power supply input end or a voltage of the second low-voltage power supply input end (fig. 2/fig. 11; ¶34; ¶95), boost the second high-voltage power supply voltage to generate a positive power supply voltage (¶96), and transmit the positive power supply voltage to the first voltage regulation circuit (¶98); and wherein the first voltage regulation circuit is configured to regulate the positive power supply voltage and then generate the second positive power supply voltage, and output the second positive power supply voltage to the second gate driving circuit (¶98; ¶156).
Kong does not mention that the high-voltage display device comprises a second circuit board, such that the second circuit board comprises a second high voltage power supply input end, a second medium-voltage power supply input end, and a second low voltage power supply input end.
Kuo teaches a driver chip (fig. 3; ¶21) in a display device, wherein the driver chip comprises a charge pump circuit (fig. 3, item 60; ¶21); the display device comprises a second circuit board (fig. 3, item 2), a second gate driving circuit (fig. 3, items 22 and 24; ¶21), and a second display screen (fig. 3, item 1); the second circuit board comprises: a second high-voltage power supply input end (fig. 3, item VSP), a second medium-voltage power supply input end (fig. 3, item VCC), and a second low-voltage power supply input end (fig. 3, item VSN).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the configuration solution of a driver chip in a display device of Kong, such that the high-voltage display device comprises a second circuit board, resulting in the second circuit board comprises a second high voltage power supply input end, a second medium-voltage power supply input end, and a second low voltage power supply input end, as taught by Kuo so as to provide an implementation method of the components.
With respect to Claim 20, claim 19 is incorporated, Kong teaches wherein in a process in which the driver chip performs the second configuration solution, the first control end is configured to receive the first control signal to turn on the first voltage boost circuit (fig. 2/11, CTRL1/ENB1 and CTL2/ENB2; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2).
With respect to Claim 23, Kong teaches a display device (fig. 1, item 1000; fig. 15, item 6000; ¶26; ¶29), comprising a driver chip (fig. 1, item 1100; fig. 15, item 6100; ¶29) wherein the driver chip is configured by using a configuration solution wherein the display device is a low-voltage display device (¶31-32, the display device is a low-voltage display device when in a low-power mode) or a high-voltage display device (¶31; ¶35, the display device is a high-voltage display device when in a normal mode), and wherein: the driver chip comprises a first voltage boost circuit (fig. 1, item 1120/fig. 2/11, item 1122/4122; ¶33; ¶35) and a first voltage regulation circuit (fig. 1, item 1130; ¶33; ¶36) that are coupled, the first voltage boost circuit is configured to boost a received voltage and then transmit the boosted voltage to the first voltage regulation circuit (¶35), and the first voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage (¶36; ¶156); the configuration solution comprises a first configuration solution and a second configuration solution (¶31, first configuration: low-power mode, second configuration: normal mode); in the first configuration solution, the driver chip is configured to be used in the low voltage display device (¶31-32, the display device is a low-voltage display device when in a low-power mode); the low-voltage display device comprises a first gate driving circuit (fig. 15, item 6400; ¶123), a first display screen (fig. 15, item 6300; ¶123), and a first direct path (fig. 2/11, path connecting item VS1 to item 1131/4131); the low-voltage display device comprises a first high-voltage power supply input end, a first medium-voltage power supply input end, and a first low-voltage power supply input end (¶34, “The switching circuit 1110 may select at least one of power supply voltages VS1 and VS2 received from the outside, and the selected power supply voltage may be supplied to the boosting circuit 1120 … For brevity of description and illustration, only two power supply voltages VS1 and VS2 are illustrated in FIG. 1, but three or more power supply voltages may be supplied to the switching circuit 1110, and the inventive concepts are not limited thereto”); the first voltage regulation circuit is coupled to the first high-voltage power supply input end through the first direct path (fig. 2/11, item 1131/4131 is connected to VS1; ¶80, “the first power supply voltage VS1 is higher in level than the second power supply voltage VS2”); the first gate driving circuit is configured to provide a gate driving signal for a pixel driving circuit in the first display screen (¶138); and a first positive power supply voltage of the first gate driving circuit is less than a first high-voltage power supply voltage of the first high-voltage power supply input end (¶10, in a first mode… an absolute value of the external voltage being greater than an absolute value of the first output voltage. In a second mode… an absolute value of the second output voltage being less than an absolute value of the first voltage and less than an absolute value of the external voltage); the first high-voltage power supply input end, the first medium-voltage power supply input end, the first low-voltage power supply input end, and a first control end are all coupled to the first voltage boost circuit (fig. 2/fig. 11; ¶34); and the first control end is configured to receive a first control signal to turn on and turn off the first voltage boost circuit (fig. 2/11, CTRL1/ENB1 and CTL2/ENB2; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2); and the first voltage regulation circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end through the first direct path (fig. 2/11, VS1 is directly connected to item 1131/4131), regulate the first high-voltage power supply voltage, and then generate and output the first positive power supply voltage to the first gate driving circuit (fig. 5; ¶65, “The first power supply voltage VS1 may be applied to a first, or source terminal of the pass transistor PT, and the output voltage VO1/VO2 may be output through a second, or drain terminal of the pass transistor PT”).
Kong does not mention that the low-voltage display device comprises a first circuit board, such that the first circuit board comprises a first high voltage power supply input end, a first medium-voltage power supply input end, and a first low voltage power supply input end.
Kuo teaches a driver chip (fig. 3; ¶21) in a display device, wherein the driver chip comprises a charge pump circuit (fig. 3, item 60; ¶21); the display device comprises a first circuit board (fig. 3, item 2), a first gate driving circuit (fig. 3, items 22 and 24; ¶21), and a first display screen (fig. 3, item 1); the first circuit board comprises: a first high-voltage power supply input end (fig. 3, item VSP), a first medium-voltage power supply input end (fig. 3, item VCC), and a first low-voltage power supply input end (fig. 3, item VSN).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Kong, such that the low-voltage display device comprises a first circuit board, resulting in the first circuit board comprises a first high voltage power supply input end, a first medium-voltage power supply input end, and a first low voltage power supply input end, as taught by Kuo so as to provide an implementation method of the components.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kong, Kuo, and Ju as applied to claim 8 above, and further in view of Duan et al. (Pub. No.: CN 102982780A) hereinafter referred to as Duan as cited on the IDS dated May 12, 2025.
With respect to Claim 9, claim 8 is incorporated, Kong, Kuo, and Ju combined do not explicitly teach wherein the driver chip comprises a first pin, a second pin, a third pin, a fourth pin, and a fifth pin, the first pin is coupled to the first high-voltage power supply input end, the second pin is coupled to the first medium voltage power supply input end, the third pin is coupled to the first low-voltage power supply input end, the fourth pin is coupled to the first direct path and the first end of the first capacitor, and the fifth pin is coupled to a first positive power supply voltage end of the first gate driving circuit and the first end of the second capacitor.
Duan teaches a configuration solution of a driver chip (fig. 2, item 201; ¶30) in a display device (¶27); wherein the driver chip comprises a first pin (fig. 2, pin of item 201 connected to AVDD,AVEE connected to item 203’ to item 202), a second pin (fig. 2, pin of item 201 connected to VCI,GND to item 202), a third pin (fig. 2, pin of item 201 connected to GND), a fourth pin (fig. 2, pin of item 201 connected to AVDD and item 203), and a fifth pin (fig. 2, pin of item 201 connected to AVDD), the first pin is coupled to the first high-voltage power supply input end (fig. 2, pin of item 201 connected to AVDD,AVEE connected to item 203’ to item 202), the second pin is coupled to the first medium voltage power supply input end (fig. 2, pin of item 201 connected to VCI,GND to item 202), the third pin is coupled to the first low-voltage power supply input end (fig. 2, pin of item 201 connected to GND), the fourth pin is coupled to the first direct path and the first end of the first component (fig. 2, via pin of item 201 connected to AVDD and item 203 and connection components), and the fifth pin (fig. 2, pin of item 201 connected to AVDD) is coupled to a first positive power supply voltage end of a first gate driving circuit (fig. 2, item 205 via item 203) and a first end of the second component (fig. 2, via item 203 and connection components).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined configuration solution of a driver chip in a display device of Kong, Kuo, and Ju, such that the components correspond to the capacitors, resulting in wherein the driver chip comprises a first pin, a second pin, a third pin, a fourth pin, and a fifth pin, the first pin is coupled to the first high-voltage power supply input end, the second pin is coupled to the first medium voltage power supply input end, the third pin is coupled to the first low-voltage power supply input end, the fourth pin is coupled to the first direct path and the first end of the first capacitor, and the fifth pin is coupled to a first positive power supply voltage end of the first gate driving circuit and the first end of the second capacitor, as taught by Duan so as to reduce the circuit area and at the same time eliminate the need for an expensive high-voltage process and reduce production costs (¶9).
Claims 8, 10-17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kong and Kuo as applied to claims 1 and 19 above, and further in view of Park et al. (Pub. No.: US 2023/0163690 A1) hereinafter referred to as Park.
With respect to Claim 8, claim 1 is incorporated, Kong and Kuo combined do not teach wherein the first circuit board further comprises a first capacitor, a second capacitor, and a first reference ground voltage end; wherein a first end of the first capacitor is coupled between the first voltage boost circuit and the first voltage regulation circuit, and a second end of the first capacitor is coupled to the first reference ground voltage end; and wherein a first end of the second capacitor is coupled between the first voltage regulation circuit and the first gate driving circuit, and a second end of the second capacitor is coupled to the first reference ground voltage end.
Park teaches a display device (fig. 2, item 200; ¶12) comprising: a first circuit board (fig. 2, item 204) and a chip (fig. 2, item 212; ¶14) comprising: dual power supply device (fig. 2, item 206; ¶14); wherein the chip further comprises a negative voltage conversion circuit (fig. 3, item 310; ¶27, “operation of the switching converter 310 controls generation of both the positive-bias output voltage (V.sub.POS_BIAS) and the negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334” – item 310 is a negative voltage conversion circuit because it controls generation of the negative input voltage NV.sub.IN), a first voltage boost circuit (fig. 3, item 325; ¶27), and a first voltage regulation circuit (fig. 3, item 338; ¶28) that are sequentially coupled in series, wherein the first circuit board further comprises a first capacitor (fig. 3, item 336), a second capacitor (fig. 3, item 342), and a first reference ground voltage end (fig. 3, item 308); wherein a first end of the first capacitor (fig. 3, item 336) is coupled between the first voltage boost circuit (fig. 3, components of item 325) and the first voltage regulation circuit (fig. 3, item 338), and a second end of the first capacitor is coupled to the first reference ground voltage end (fig. 3, item 308); and wherein a first end of the second capacitor is coupled between the first voltage regulation circuit (fig. 3, item 338) and the first output (fig. 3, item VNEG_BIAS), and a second end of the second capacitor is coupled to the first reference ground voltage end (fig. 3, item 308).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date to modify the combined configuration solution of a driver chip in a display device of Kong and Kuo such that the negative voltage conversion circuit of Park is connected to an input voltage VS1 of the first voltage boost circuit of Kong, such that VS2 of the first voltage boost circuit corresponds to the first medium-voltage power supply input end, such that CLK2/ENB2 of the first voltage boost circuit corresponds to a second control end, the first output VNEG_BIAS corresponds to the gate driving circuit resulting in wherein the driver chip further comprises a negative voltage conversion circuit, a second voltage boost circuit, and a second voltage regulation circuit that are sequentially coupled in series, the negative voltage conversion circuit is configured to convert the received first high-voltage power supply voltage into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit, the second voltage boost circuit is configured to boost the negative first high-voltage power supply voltage and transmit the boosted voltage to the second voltage regulation circuit, and the second voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage; wherein the low-voltage display device further comprises a second direct path, the second voltage regulation circuit is coupled to the negative voltage conversion circuit through the second direct path, and an absolute value of a first negative power supply voltage of the first gate driving circuit is less than the first high-voltage power supply voltage; and wherein the first configuration solution further comprises: the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end, convert the received first high-voltage power supply voltage into the negative first high-voltage power supply voltage, and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit and the second direct circuit; the negative voltage conversion circuit, the first medium-voltage power supply input end, the first low-voltage power supply input end, and a second control end are all coupled to the second voltage boost circuit; and the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit; and the second voltage regulation circuit is configured to receive the negative first high-voltage power supply voltage through the second direct path, regulate the negative first high voltage power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage to the first gate driving circuit, as taught by Park so as to reduce power consumption in the process of generating a voltage that the display driver integrated circuit uses to drive the display device (¶5).
With respect to Claim 10, claim 1 is incorporated, Kong does not mention wherein the driver chip further comprises a negative voltage conversion circuit, a second voltage boost circuit, and a second voltage regulation circuit that are sequentially coupled in series, the negative voltage conversion circuit is configured to convert the received first high-voltage power supply voltage into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit, the second voltage boost circuit is configured to boost the negative first high-voltage power supply voltage and transmit the boosted voltage to the second voltage regulation circuit, and the second voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage; wherein the low-voltage display device further comprises a second direct path, the second voltage regulation circuit is coupled to the negative voltage conversion circuit through the second direct path, and an absolute value of a first negative power supply voltage of the first gate driving circuit is less than the first high-voltage power supply voltage; and wherein the first configuration solution further comprises: the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end, convert the received first high-voltage power supply voltage into the negative first high-voltage power supply voltage, and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit and the second direct circuit; the negative voltage conversion circuit, the first medium-voltage power supply input end, the first low-voltage power supply input end, and a second control end are all coupled to the second voltage boost circuit; and the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit; and the second voltage regulation circuit is configured to receive the negative first high-voltage power supply voltage through the second direct path, regulate the negative first high voltage power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage to the first gate driving circuit.
Park teaches a display device (fig. 2, item 200; ¶12) comprising: a chip (fig. 2, item 212; ¶14) comprising: dual power supply device (fig. 2, item 206; ¶14); wherein the chip further comprises a negative voltage conversion circuit (fig. 3, item 310; ¶27, “operation of the switching converter 310 controls generation of both the positive-bias output voltage (V.sub.POS_BIAS) and the negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334” – item 310 is a negative voltage conversion circuit because it controls generation of the negative input voltage NV.sub.IN), a second voltage boost circuit (fig. 3, item 325; ¶27), and a second voltage regulation circuit (fig. 3, item 338; ¶28) that are sequentially coupled in series, the negative voltage conversion circuit is configured to convert the received first high-voltage power supply voltage into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit (¶19, “the switching converter 310 may include a buck-boost switching converter that is configured to reverse a polarity of the input voltage (V.sub.IN)”; ¶27, “the negative input voltage (NV.sub.IN) is generated based on a signal output from the second switching node 312 of the switching converter 310”), the second voltage boost circuit is configured to boost the negative first high-voltage power supply voltage and transmit the boosted voltage to the second voltage regulation circuit (¶25, “The inverting charge pump 325 is configured to generate a negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334 of the linear voltage regulator 338”), and the second voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage (¶28); wherein the display device further comprises a second direct path (fig. 3, the second direct path is from node 312 to node 328 to node 334), the second voltage regulation circuit is coupled to the negative voltage conversion circuit through the second direct path (fig. 3), and an absolute value of a first negative power supply voltage is less than the first high-voltage power supply voltage (¶27, “the negative input voltage (NV.sub.IN) is generated at the linear voltage regulator input node 334, because the absolute voltage level is less than the absolute voltage level at the first diode 330”; ¶28 – therefore at node 340 a first negative power supply voltage is less than the first high-voltage power supply voltage); wherein the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end (Fig. 3, Vin supplied by item 302 to Vin of item 310; ¶15), convert the received first high-voltage power supply voltage into the negative first high-voltage power supply voltage (¶19, “the switching converter 310 may include a buck-boost switching converter that is configured to reverse a polarity of the input voltage (V.sub.IN)”), and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit (¶27, “the negative input voltage (NV.sub.IN) is generated based on a signal output from the second switching node 312 of the switching converter 310”) and the second direct circuit/second direct path (fig. 3); the negative voltage conversion circuit (fig. 3, item 310), the first low-voltage power supply input end (fig. 3, item 308), are all coupled to the second voltage boost circuit (fig. 3, item 325: second voltage boost circuit); and the second voltage regulation circuit (fig. 3, item 338) is configured to receive the negative first high-voltage power supply voltage through the second direct path (fig. 3, the second direct path is from node 312 to node 328 to node 334), regulate the negative first high voltage power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage (¶28).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date to modify the combined configuration solution of a driver chip in a display device of Kong and Kuo such that the negative voltage conversion circuit of Park is connected to an input voltage VS1 of another voltage boost circuit of Kong, such that VS2 of the another voltage boost circuit corresponds to the first medium-voltage power supply input end, such that CLK2/ENB2 of the another voltage boost circuit corresponds to a second control end, wherein the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit resulting in wherein the driver chip further comprises a negative voltage conversion circuit, a second voltage boost circuit, and a second voltage regulation circuit that are sequentially coupled in series, the negative voltage conversion circuit is configured to convert the received first high-voltage power supply voltage into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit, the second voltage boost circuit is configured to boost the negative first high-voltage power supply voltage and transmit the boosted voltage to the second voltage regulation circuit, and the second voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage; wherein the low-voltage display device further comprises a second direct path, the second voltage regulation circuit is coupled to the negative voltage conversion circuit through the second direct path, and an absolute value of a first negative power supply voltage of the first gate driving circuit is less than the first high-voltage power supply voltage; and wherein the first configuration solution further comprises: the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end, convert the received first high-voltage power supply voltage into the negative first high-voltage power supply voltage, and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit and the second direct circuit; the negative voltage conversion circuit, the first medium-voltage power supply input end, the first low-voltage power supply input end, and a second control end are all coupled to the second voltage boost circuit; and the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit; and the second voltage regulation circuit is configured to receive the negative first high-voltage power supply voltage through the second direct path, regulate the negative first high voltage power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage to the first gate driving circuit, as taught by Park so as to reduce power consumption in the process of generating a voltage that the display driver integrated circuit uses to drive the display device (¶5).
With respect to Claim 11, claim 10 is incorporated, Kong teaches wherein in a process in which the driver chip performs the first configuration solution, the second control end is configured to receive the second control signal to turn off the second voltage boost circuit (fig. 2/11, CTL2/ENB2 of the second voltage boost circuit; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2 which is the second control signal).
With respect to Claim 12, claim 11 is incorporated, Kong teaches wherein the driver chip comprises a second register (fig. 11, item 4150 corresponding to controls of the second voltage booster circuit; ¶95), and the second register is configured to transmit the second control signal to the second control end (fig. 11, item 4150 corresponding to controls of the second voltage booster circuit is a register since a first control signal is transmitted to the first voltage boost circuit).
With respect to Claim 13, claim 10 is incorporated, Kong teaches wherein a second direct path comprises a second resistor (fig. 2/11, the second direct path from item VS1 of the second voltage boost circuit to the voltage regulator has a line resistance and also acts a first resistor).
With respect to Claim 14, claim 13 is incorporated, Kong teaches wherein the second resistor comprises a 0-ohm resistor (fig. 2/11, the second direct path from item VS1 of the second voltage boost circuit to the voltage regulator has a line resistance and also acts a first resistor, in this case it is 0 ohm).
With respect to Claim 15, claim 10 is incorporated, Kong teaches wherein the second direct path comprises a second signal line (fig. 2/11 of the second voltage boost circuit).
With respect to Claim 16, claim 10 is incorporated, Kong teaches wherein the second direct path is integrated into the driver chip (fig. 2/11 of the second voltage boost circuit; ¶45; ¶95).
With respect to Claim 17, claim 10 is incorporated, Kong and Kuo do not teach wherein the first circuit board further comprises a third capacitor, a fourth capacitor, a fifth capacitor, and a second reference ground voltage end; wherein a first end of the third capacitor is coupled between the negative voltage conversion circuit and the second voltage boost circuit, and a second end of the third capacitor is coupled to the second reference ground voltage end; wherein a first end of the fourth capacitor is coupled between the second voltage boost circuit and the second voltage regulation circuit, and a second end of the fourth capacitor is coupled to the second reference ground voltage end; and wherein a first end of the fifth capacitor is coupled between the second voltage regulation circuit and the first gate driving circuit, and a second end of the fifth capacitor is coupled to the second reference ground voltage end.
Park teaches a display device (fig. 2, item 200; ¶12) comprising: a chip (fig. 2, item 212; ¶14) comprising: dual power supply device (fig. 2, item 206; ¶14); wherein the driver chip further comprises a negative voltage conversion circuit (fig. 3, item 310; ¶27, “operation of the switching converter 310 controls generation of both the positive-bias output voltage (V.sub.POS_BIAS) and the negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334” – item 310 is a negative voltage conversion circuit because it controls generation of the negative input voltage NV.sub.IN), a second voltage boost circuit (fig. 3, item 325; ¶27), and a second voltage regulation circuit (fig. 3, item 338; ¶28) that are sequentially coupled in series, the negative voltage conversion circuit is configured to convert the received first high-voltage power supply voltage into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit (¶19, “the switching converter 310 may include a buck-boost switching converter that is configured to reverse a polarity of the input voltage (V.sub.IN)”; ¶27, “the negative input voltage (NV.sub.IN) is generated based on a signal output from the second switching node 312 of the switching converter 310”), the second voltage boost circuit is configured to boost the negative first high-voltage power supply voltage and transmit the boosted voltage to the second voltage regulation circuit (¶25, “The inverting charge pump 325 is configured to generate a negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334 of the linear voltage regulator 338”), and the second voltage regulation circuit is configured to regulate the received voltage and then output the regulated voltage (¶28); wherein the display device further comprises a second direct path (fig. 3, the second direct path is from node 312 to node 328 to node 334), the second voltage regulation circuit is coupled to the negative voltage conversion circuit through the second direct path (fig. 3), and an absolute value of a first negative power supply voltage is less than the first high-voltage power supply voltage (¶27, “the negative input voltage (NV.sub.IN) is generated at the linear voltage regulator input node 334, because the absolute voltage level is less than the absolute voltage level at the first diode 330”; ¶28 – therefore at node 340 a first negative power supply voltage is less than the first high-voltage power supply voltage); wherein the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end (Fig. 3, Vin supplied by item 302 to Vin of item 310; ¶15), convert the received first high-voltage power supply voltage into the negative first high-voltage power supply voltage (¶19, “the switching converter 310 may include a buck-boost switching converter that is configured to reverse a polarity of the input voltage (V.sub.IN)”), and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit (¶27, “the negative input voltage (NV.sub.IN) is generated based on a signal output from the second switching node 312 of the switching converter 310”) and the second direct circuit/second direct path (fig. 3); the negative voltage conversion circuit (fig. 3, item 310), the first low-voltage power supply input end (fig. 3, item 308), are all coupled to the second voltage boost circuit (fig. 3, item 325: second voltage boost circuit); and the second voltage regulation circuit (fig. 3, item 338) is configured to receive the negative first high-voltage power supply voltage through the second direct path (fig. 3, the second direct path is from node 312 to node 328 to node 334), regulate the negative first high voltage power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage (¶28); wherein the first circuit board further comprises a third capacitor (fig. 3, item CF), a fourth capacitor (fig. 3, item 334), a fifth capacitor (fig. 3, item 342), and a second reference ground voltage end (fig. 3, item 308); wherein a first end of the third capacitor is coupled between the negative voltage conversion circuit (fig. 3, at node 312) and the second voltage boost circuit (fig. 3), and a second end of the third capacitor (fig. 3, at node 328) is coupled to the second reference ground voltage end (fig. 3, via item 330); wherein a first end of the fourth capacitor (fig. 3, item 336) is coupled between the second voltage boost circuit (fig. 3, components of item 325) and the second voltage regulation circuit (fig. 3, item 338), and a second end of the fourth capacitor is coupled to the second reference ground voltage end (fig. 3, item 308); and wherein a first end of the fifth capacitor (fig. 3, at node 340) is coupled between the second voltage regulation circuit and VNEG_BIAS, and a second end of the fifth capacitor is coupled to the second reference ground voltage end (fig. 3, item 308).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date to modify the combined configuration solution of a driver chip in a display device of Kong and Kuo such that the negative voltage conversion circuit of Park is connected to an input voltage VS1 of another voltage boost circuit of Kong, such that VS2 of the another voltage boost circuit corresponds to the first medium-voltage power supply input end, such that CLK2/ENB2 of the another voltage boost circuit corresponds to a second control end, wherein the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit, and VNEG_BIAS corresponds to the signal transmitted to the first gate driving circuit resulting in wherein the first circuit board further comprises a third capacitor, a fourth capacitor, a fifth capacitor, and a second reference ground voltage end; wherein a first end of the third capacitor is coupled between the negative voltage conversion circuit and the second voltage boost circuit, and a second end of the third capacitor is coupled to the second reference ground voltage end; wherein a first end of the fourth capacitor is coupled between the second voltage boost circuit and the second voltage regulation circuit, and a second end of the fourth capacitor is coupled to the second reference ground voltage end; and wherein a first end of the fifth capacitor is coupled between the second voltage regulation circuit and the first gate driving circuit, and a second end of the fifth capacitor is coupled to the second reference ground voltage end, as taught by Park so as to reduce power consumption in the process of generating a voltage that the display driver integrated circuit uses to drive the display device (¶5).
With respect to Claim 21, claim 19 is incorporated, Kong and Kuo do not teach wherein an absolute value of a second negative power supply voltage of the second gate driving circuit is greater than the second high-voltage power supply voltage; and wherein the second configuration solution further comprises: a negative voltage conversion circuit is configured to receive the second high voltage power supply voltage of the second high-voltage power supply input end, convert the received second high-voltage power supply voltage into a negative second high-voltage power supply voltage, and transmit the negative second high-voltage power supply voltage to a second voltage boost circuit; the second voltage boost circuit is configured to receive the negative second high voltage power supply voltage and at least one of the voltage of the second medium-voltage power supply input end or the voltage of the second low-voltage power supply input end, boost the negative second high-voltage power supply voltage to generate a negative power supply voltage, and transmit the negative power supply voltage to a second voltage regulation circuit; and the second voltage regulation circuit is configured to regulate the negative power supply voltage and then generate the second negative power supply voltage, and output the second negative power supply voltage to the second gate driving circuit.
Park teaches a display device (fig. 2, item 200; ¶12) comprising: a chip (fig. 2, item 212; ¶14) comprising: dual power supply device (fig. 2, item 206; ¶14); wherein the chip further comprises a negative voltage conversion circuit (fig. 3, item 310; ¶27, “operation of the switching converter 310 controls generation of both the positive-bias output voltage (V.sub.POS_BIAS) and the negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334” – item 310 is a negative voltage conversion circuit because it controls generation of the negative input voltage NV.sub.IN), a second voltage boost circuit (fig. 3, item 325; ¶27) and a second voltage regulation circuit (fig. 3, item 338; ¶28) that are sequentially coupled in series, the negative voltage conversion circuit is configured to receive the first high-voltage power supply voltage of the first high-voltage power supply input end, convert the received first high-voltage power supply into a negative first high-voltage power supply voltage and transmit the negative first high-voltage power supply voltage to the second voltage boost circuit (¶19, “the switching converter 310 may include a buck-boost switching converter that is configured to reverse a polarity of the input voltage (V.sub.IN)”; ¶27, “the negative input voltage (NV.sub.IN) is generated based on a signal output from the second switching node 312 of the switching converter 310”), the second voltage boost circuit is configured to receive the negative first high voltage power supply voltage and at least one of the voltage of the first medium-voltage power supply input end or the voltage of the first low-voltage power supply input end, boost the negative first high-voltage power supply voltage to generate a negative power supply voltage and transmit the negative power supply voltage to the second voltage regulation circuit (¶25, “The inverting charge pump 325 is configured to generate a negative input voltage (NV.sub.IN) at the linear voltage regulator input node 334 of the linear voltage regulator 338”), and the second voltage regulation circuit is configured to regulate the negative power supply voltage and then generate the first negative power supply voltage, and output the first negative power supply voltage (¶28).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date to modify the combined configuration solution of a driver chip in a display device of Kong and Kuo such that in a normal mode the negative voltage conversion circuit of Park is connected to an input voltage VS1 of another voltage boost circuit of Kong, such that VS2 of the another voltage boost circuit corresponds to a second medium-voltage power supply input end, such that CLK2/ENB2 of the another voltage boost circuit corresponds to a second control end, wherein the second control end is configured to receive a second control signal to turn on and turn off the second voltage boost circuit wherein in the normal mode a first negative power supply voltage corresponds to a second negative power supply voltage, a first high-voltage power supply corresponds to second high-voltage power supply voltage, first medium-voltage power supply corresponds to second medium-voltage power supply, and first low-voltage power supply corresponds to second low-voltage power supply resulting in wherein an absolute value of a second negative power supply voltage of the second gate driving circuit is greater than the second high-voltage power supply voltage; and wherein the second configuration solution further comprises: a negative voltage conversion circuit is configured to receive the second high voltage power supply voltage of the second high-voltage power supply input end, convert the received second high-voltage power supply voltage into a negative second high-voltage power supply voltage, and transmit the negative second high-voltage power supply voltage to a second voltage boost circuit; the second voltage boost circuit is configured to receive the negative second high voltage power supply voltage and at least one of the voltage of the second medium-voltage power supply input end or the voltage of the second low-voltage power supply input end, boost the negative second high-voltage power supply voltage to generate a negative power supply voltage, and transmit the negative power supply voltage to a second voltage regulation circuit; and the second voltage regulation circuit is configured to regulate the negative power supply voltage and then generate the second negative power supply voltage, and output the second negative power supply voltage to the second gate driving circuit, as taught by Park so as to reduce power consumption in the process of generating a voltage that the display driver integrated circuit uses to drive the display device (¶5).
With respect to Claim 22, claim 21 is incorporated, Kong teaches wherein in a process in which the driver chip performs the second configuration solution (in a normal mode), a second control end is configured to receive a second control signal to turn on the second voltage boost circuit (fig. 2/11, CTL2/ENB2 of the second voltage boost circuit; ¶50, “in the low-power mode, the second booster 1122 may generate the second boosting voltage VB2 used for the second regulator 1132 to generate the second output voltage VO2. The operation may be executed by a control signal CTRL2. An absolute value of the second boosting voltage VB2 may be smaller than an absolute value of the first boosting voltage VB1”; ¶63 – item 1122/4122 is turned on and off according to CLK2/ENB2 or CTRL2 which is the second control signal).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kong, Kuo, and Park as applied to claim 17 above, and further in view of Duan.
With respect to Claim 18, claim 17 is incorporated, Kong, Kuo, and Park combined do not teach wherein the driver chip further comprises a sixth pin, a seventh pin, and an eighth pin, the sixth pin is coupled to the first end of the third capacitor and a first end of the second direct path, the seventh pin is coupled to the first end of the fourth capacitor and a second end of the second direct path, and the eighth pin is coupled to a first negative power supply voltage end of the first gate driving circuit.
Duan teaches a configuration solution of a driver chip (fig. 2, item 201; ¶30) in a display device (¶27); wherein the driver chip comprises a sixth pin (fig. 2, pin of item 201 connected to AVDD,AVEE and item 202), a seventh pin (fig. 2, pin of item 201 connected to VCI,GND and item 202), and an eighth pin (fig. 2, pin of item 201 connected to AVEE and item 203), the sixth pin is coupled to the first end of the third component and a first end of the second direct path (fig. 2, via pin of item 201 connected to AVDD and item 203 and various components), the seventh pin is coupled to the first end of the fourth component and a second end of the second direct path (fig. 2, via pin of item 201 connected to VCI,GND and item 202 and various components), and the eighth pin is coupled to a first negative power supply voltage end of the first gate driving circuit (fig. 2, pin of item 201 connected to AVEE and item 203 to item 205).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined configuration solution of a driver chip in a display device of Kong, Kuo, and Park, such that the components correspond to the capacitors, resulting in wherein the driver chip further comprises a sixth pin, a seventh pin, and an eighth pin, the sixth pin is coupled to the first end of the third capacitor and a first end of the second direct path, the seventh pin is coupled to the first end of the fourth capacitor and a second end of the second direct path, and the eighth pin is coupled to a first negative power supply voltage end of the first gate driving circuit, as taught by Duan so as to reduce the circuit area and at the same time eliminate the need for an expensive high-voltage process and reduce production costs (¶9).
Conclusion
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/DONNA V Bocar/ Examiner, Art Unit 2621