CTNF 19/091,628 CTNF 86657 DETAILED ACTION Claims 21-40 are pending. Claims 1-20 are cancelled. Priority: 12/10/2019(Continuation of 16/709,798) Assignee: Intel Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim (s) 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claim (s) 1-20 of U.S. Patent No. 11,675,716 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variations of each other as shown below . 19/091,628(instant) 11,675,716(parent) An apparatus comprising: a command and address (CA) interface configured to couple with a memory device; a DQ interface configured to couple with the memory device; and input/output (I/O) training circuitry configured to couple with the CA interface, the DQ interface and a controller, wherein the I/O training circuitry is also configured to: cause a CA pattern to be output through a command bus of the CA interface, wherein depending on whether the memory device was triggered to be in a first command bus training mode or a second command bus training mode, the I/O training circuitry is to: receive a sampled CA pattern from the memory device through a data bus of the DQ interface based on the memory device triggered to enter the first command bus training mode; or receive a compressed value from the memory device through the data bus of the DQ interface, the compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device triggered to enter the second command bus training mode; use the sampled CA pattern or the compressed value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern output does not match the sampled CA pattern. (additionally claim 29, 36) A memory controller comprising: a command logic to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode to train a command and address (CA) interface of the memory device; and input/output (I/O) training circuitry to cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device, the I/O training circuitry to also: compress a sampled CA pattern received from the memory device via a data bus coupled with a DQ interface of the memory device to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the command logic; or forward, to the command logic, a second compressed value received from the memory device via the data bus, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode. 2. The memory controller of claim 1, further comprising: the command logic to use the first compressed value or the second compressed value to determine whether the CA pattern sent via the command bus matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern sent does not match the sampled CA pattern. 22 . The apparatus of claim 21, further comprising the I/O training circuitry to: compress the received sampled CA pattern to generate a second compressed value based on the memory device triggered to enter the first command bus training mode. (additionally claim 30, 37) (claim 1) a second compressed value received from the memory device via the data bus, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode. 23 . The apparatus of claim 22, comprising: the I/O training circuitry configured to cause the CA pattern to be output through an even number of signal lines included in the command bus of the CA interface; and the compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, output through the even number of signal lines, matching the sampled CA pattern. (additionally claim 31, 38) 3. The memory controller of claim 1, comprising: the I/O training circuitry to generate the CA pattern to be output via an even number of signal lines included in the command bus; and the first compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, sent via the even number of signal lines, matching the sampled CA pattern. 24 . The apparatus of claim 23, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device to have circuitry to generate the even parity value of 0 from the sampled CA pattern to represent the sampled CA pattern that was compressed at the memory device and send the even parity value of 0 through the data bus of the DQ interface to provide the compressed value to the I/O training circuitry. (additionally claim 32, 39) 4. The memory controller of claim 3, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device having circuitry to generate the even parity value of 0 from the sampled CA pattern and indicate the even parity value of 0 for the sampled CA pattern via the data bus. 25 . The apparatus of claim 23, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry, to generate the second compressed value, is configured to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. (additionally claim 33, 40) 5. The memory controller of claim 3, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. 26 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value, wherein the signature value is to be used to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern to cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 34) 6. The memory controller of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O training circuitry to include circuitry to calculate a cyclic redundancy check (CRC) value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the CRC value to the command logic; and the command logic to: use the CRC value to determine whether the CA pattern sent via the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern is determined to not match the sample CA pattern. 27 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value and forward the signature value to the controller, wherein the controller is to use the signature value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 35) 7. The memory controller of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O training circuitry to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the signature value to the command logic; and the command logic to: use the signature value to determine whether the CA pattern sent via the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern is determined to not match the sample CA pattern. 28 . The apparatus of claim 21, the CA pattern to be output through the command bus of the CA interface comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. 8. The memory controller of claim 1, the CA pattern to be output via the command bus comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode . 08-34 AIA Claim (s) 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claim (s) 1-20 of U.S. Patent No. 12,093,195 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims . 19/091,628(instant) 12,093,195(parent) An apparatus comprising: a command and address (CA) interface configured to couple with a memory device; a DQ interface configured to couple with the memory device; and input/output (I/O) training circuitry configured to couple with the CA interface, the DQ interface and a controller, wherein the I/O training circuitry is also configured to: cause a CA pattern to be output through a command bus of the CA interface, wherein depending on whether the memory device was triggered to be in a first command bus training mode or a second command bus training mode, the I/O training circuitry is to: receive a sampled CA pattern from the memory device through a data bus of the DQ interface based on the memory device triggered to enter the first command bus training mode; or receive a compressed value from the memory device through the data bus of the DQ interface, the compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device triggered to enter the second command bus training mode; use the sampled CA pattern or the compressed value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern output does not match the sampled CA pattern. (additionally claim 29, 36) 1. An apparatus comprising: a controller logic configured to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode to train a command and address (CA) interface of the memory device; and input/output (I/O) circuitry configured to: cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device; and receive a sampled CA pattern from the memory device via a data bus coupled with a DQ interface of the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the controller logic; or receive a second compressed value from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode and forward the second compressed value to the controller logic. 2. The apparatus of claim 1, further comprising: the controller logic to use the first compressed value or the second compressed value to determine whether the CA pattern output via the command bus matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern output via the command bus does not match the sampled CA pattern. 22 . The apparatus of claim 21, further comprising the I/O training circuitry to: compress the received sampled CA pattern to generate a second compressed value based on the memory device triggered to enter the first command bus training mode. (additionally claim 30, 37) (claim 1) receive a second compressed value from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode. 23 . The apparatus of claim 22, comprising: the I/O training circuitry configured to cause the CA pattern to be output through an even number of signal lines included in the command bus of the CA interface; and the compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, output through the even number of signal lines, matching the sampled CA pattern. (additionally claim 31, 38) 3. The apparatus of claim 1, comprising: the I/O circuitry configured to cause the CA pattern to be output via an even number of signal lines included in the command bus; and the first compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, output via the even number of signal lines, matching the sampled CA pattern. 24 . The apparatus of claim 23, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device to have circuitry to generate the even parity value of 0 from the sampled CA pattern to represent the sampled CA pattern that was compressed at the memory device and send the even parity value of 0 through the data bus of the DQ interface to provide the compressed value to the I/O training circuitry. (additionally claim 32, 39) 4. The apparatus of claim 3, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device to have circuitry to generate the even parity value of 0 from the sampled CA pattern and indicate the even parity value of 0 for the sampled CA pattern via the data bus to provide the second compressed value to the I/O circuitry. 25 . The apparatus of claim 23, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry, to generate the second compressed value, is configured to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. (additionally claim 33, 40) 5. The apparatus of claim 3, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O circuitry, to generate the first compressed value, is configured to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. 26 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value, wherein the signature value is to be used to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern to cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 34) 6. The apparatus of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O circuitry configured to include circuitry to calculate a cyclic redundancy check (CRC) value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the CRC value to the controller logic; and the controller logic configured to: use the CRC value to determine whether the CA pattern output via the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern is determined to not match the sample CA pattern. 27 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value and forward the signature value to the controller, wherein the controller is to use the signature value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 35) 7. The apparatus of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the signature value to the controller logic; and the controller logic configured to: use the signature value to determine whether the CA pattern output via the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface of the memory device if the CA pattern is determined to not match the sample CA pattern. 28 . The apparatus of claim 21, the CA pattern to be output through the command bus of the CA interface comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. 8. The apparatus of claim 1, the CA pattern to be output via the command bus comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode . 08-34 AIA Claim (s) 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claim (s) 1-20 of U.S. Patent No. 12,417,195 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims . 19/091,628(instant) 12,417,195(parent) An apparatus comprising: a command and address (CA) interface configured to couple with a memory device; a DQ interface configured to couple with the memory device; and input/output (I/O) training circuitry configured to couple with the CA interface, the DQ interface and a controller, wherein the I/O training circuitry is also configured to: cause a CA pattern to be output through a command bus of the CA interface, wherein depending on whether the memory device was triggered to be in a first command bus training mode or a second command bus training mode, the I/O training circuitry is to: receive a sampled CA pattern from the memory device through a data bus of the DQ interface based on the memory device triggered to enter the first command bus training mode; or receive a compressed value from the memory device through the data bus of the DQ interface, the compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device triggered to enter the second command bus training mode; use the sampled CA pattern or the compressed value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern output does not match the sampled CA pattern. (additionally claim 29, 36) 1. An apparatus comprising: a controller configured to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode to train a command and address (CA) interface arranged to couple with the memory device; and input/output (I/O) circuitry configured to: cause a CA pattern to be output through a command bus of the CA interface; and receive a sampled CA pattern from the memory device through a data bus of a DQ interface arranged to couple with the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device triggered to enter the first command bus training mode and forward the first compressed value to the controller; or receive a second compressed value from the memory device through the data bus of the DQ interface, the second compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device triggered to enter the second command bus training mode and forward the second compressed value to the controller. 2. The apparatus of claim 1, further comprising: the controller to use the first compressed value or the second compressed value to determine whether the CA pattern output through the command bus matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern output through the command bus does not match the sampled CA pattern. 22 . The apparatus of claim 21, further comprising the I/O training circuitry to: compress the received sampled CA pattern to generate a second compressed value based on the memory device triggered to enter the first command bus training mode. (additionally claim 30, 37) (claim 1) receive a sampled CA pattern from the memory device through a data bus of a DQ interface arranged to couple with the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device triggered to enter the first command bus training mode. 23 . The apparatus of claim 22, comprising: the I/O training circuitry configured to cause the CA pattern to be output through an even number of signal lines included in the command bus of the CA interface; and the compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, output through the even number of signal lines, matching the sampled CA pattern. (additionally claim 31, 38) 3. The apparatus of claim 1, comprising: the I/O circuitry configured to cause the CA pattern to be output through an even number of signal lines included in the command bus; and the first compressed value or the second compressed value are an even parity value of 0 based on the CA pattern, output through the even number of signal lines, matching the sampled CA pattern. 24 . The apparatus of claim 23, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device to have circuitry to generate the even parity value of 0 from the sampled CA pattern to represent the sampled CA pattern that was compressed at the memory device and send the even parity value of 0 through the data bus of the DQ interface to provide the compressed value to the I/O training circuitry. (additionally claim 32, 39) 4. The apparatus of claim 3, comprising: the second command bus training mode is a command address training mode (CATM); and the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard, the SDRAM device to have circuitry to generate the even parity value of 0 from the sampled CA pattern and indicate the even parity value of 0 for the sampled CA pattern through the data bus of the DQ interface to provide the second compressed value to the I/O circuitry. 25 . The apparatus of claim 23, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry, to generate the second compressed value, is configured to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. (additionally claim 33, 40) 5. The apparatus of claim 3, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O circuitry, to generate the first compressed value, is configured to include one or more exclusive OR (XOR) gates to generate the even parity value of 0 from the sampled CA pattern received from the SDRAM device. 26 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value, wherein the signature value is to be used to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern to cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 34) 6. The apparatus of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O circuitry configured to include circuitry to calculate a cyclic redundancy check (CRC) value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the CRC value to the controller; and the controller configured to: use the CRC value to determine whether the CA pattern output through the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. 27 . The apparatus of claim 22, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; and the I/O training circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the second compressed value and forward the signature value to the controller, wherein the controller is to use the signature value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. (additionally claim 35) 7. The apparatus of claim 1, comprising: the first command bus training mode is a command bus training (CBT) mode; the memory device is a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate standard; the I/O circuitry configured to include a multi-input shift register to generate a signature value from the sampled CA pattern received from the SDRAM device to generate the first compressed value and forward the signature value to the controller; and the controller configured to: use the signature value to determine whether the CA pattern output through the command bus matches the sampled CA pattern, and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern is determined to not match the sample CA pattern. 28 . The apparatus of claim 21, the CA pattern to be output through the command bus of the CA interface comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. 8. The apparatus of claim 1, the CA pattern to be output through the command bus comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. Allowable Subject Matter Claims 21-40 contain allowable subject matter. The following is an examiner’s statement of reasons for stating allowable subject matter. “…An apparatus comprising: a command and address (CA) interface configured to couple with a memory device; a DQ interface configured to couple with the memory device; and input/output (I/O) training circuitry configured to couple with the CA interface, the DQ interface and a controller, wherein the I/O training circuitry is also configured to: cause a CA pattern to be output through a command bus of the CA interface, wherein depending on whether the memory device was triggered to be in a first command bus training mode or a second command bus training mode, the I/O training circuitry is to: receive a sampled CA pattern from the memory device through a data bus of the DQ interface based on the memory device triggered to enter the first command bus training mode; or receive a compressed value from the memory device through the data bus of the DQ interface, the compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device triggered to enter the second command bus training mode; use the sampled CA pattern or the compressed value to determine whether the CA pattern output through the command bus of the CA interface matches the sampled CA pattern; and cause an adjustment to one or more electrical or timing parameters associated with the CA interface if the CA pattern output does not match the sampled CA pattern.…”. A related prior art is Porterfield(20090019323) where the method involves transmitting patterns of read data from a memory device to a controller though a set of read data lanes, where the pattern of the read data is transmitted in packet frames in a full unit interval. The transmitted patterns of the read data is captured at the controller. Coarse lane-to-lane skew is detected between the frames of the read data captured by the controller from respective read data lanes. The detected coarse lane-to-lane skew is utilized to alter the read data that is captured by the controller. The method utilizes an initialization system that inexpensively initializes a memory system with a memory device through high-speed bus, thus allowing gap to provide transmitting devices a chance for transition between training states and responsibility of a host controller. Another related prior art is Kostinsky et al.(20140189224) where the method involves transmitting a first pattern with a memory controller on a command/address bus (120) resulting in a dynamic (DRAM) transmitting a first value on data pins producing unique sum of one-s per byte. Signals from the data pins are sampled after the first pattern is transmitted to obtain a first sample. A second pattern is transmitted on the bus resulting in DRAM transmitting a second value on the data pins. The signals are sampled from the data pins after the second pattern is transmitted to obtain a second sample. The samples are used to generate data pin mapping. The method enables cycling through position of a single differing value of CA phase to allow a training mechanism to identify one data pin at time and generate appropriate mapping in a more efficient manner within less time, thus avoiding time and efforts spent for enabling most basic training routines to run. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Arvind Talukdar Primary Examiner Art Unit 2132 /ARVIND TALUKDAR/Primary Examiner, Art Unit 2132 Application/Control Number: 19/091,628 Page 2 Art Unit: 2132 Application/Control Number: 19/091,628 Page 3 Art Unit: 2132
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