Prosecution Insights
Last updated: April 19, 2026
Application No. 19/091,757

DISPLAY MODULE AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Mar 26, 2025
Examiner
BOGALE, AMEN W
Art Unit
2628
Tech Center
2600 — Communications
Assignee
Seiko Epson Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
78%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
338 granted / 455 resolved
+12.3% vs TC avg
Minimal +4% lift
Without
With
+4.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
29 currently pending
Career history
484
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
34.1%
-5.9% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 455 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 1. Claim(s) 1-2, 4, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bang et al (US 2023/0162670). As to claim 1, Bang teaches a display module comprising: an electro-optical device that includes a temperature detection element and is configured to display an image ([0051] The pixel P may have a structure in which a sensing current SC is output through a sensing line SL when a temperature sensing voltage TSV is applied through a data line DL. For example, as shown in FIG. 3, the pixel P may include a driving transistor DT, a switching transistor ST, a sensing transistor MT); a wiring board that includes a driving circuit configured to drive the electro-optical device ([0053] The display panel driver 120 may drive the display panel 110. To accomplish this, the display panel driver 120 may include a gate driver, a data driver, a sensing driver); and a circuit board that includes a first control circuit configured to control the driving circuit and is electrically coupled to the electro-optical device via the wiring board ([0057] The timing controller may generate a plurality of control signals and provide the generated control signals to the gate driver, the data driver, and the sensing driver to control the gate driver, the data driver, and the sensing driver), wherein the driving circuit includes a measurement circuit ([0063] at least two of the display panel driver 120, the panel temperature determiner 140, and the temperature afterimage compensator 150 may be implemented as one configuration) configured to measure a temperature of the electro-optical device based on an output signal from the temperature detection element in a flyback period of the electro-optical device ([0066] the panel temperature determiner 140 may measure the sensing currents SC flowing through the pixels P during the vertical blank period FV of the one frame 1F). As to claim 2, Bang teaches a display module comprising: an electro-optical device that includes a temperature detection element and is configured to display an image ([0051] The pixel P may have a structure in which a sensing current SC is output through a sensing line SL when a temperature sensing voltage TSV is applied through a data line DL. For example, as shown in FIG. 3, the pixel P may include a driving transistor DT, a switching transistor ST, a sensing transistor MT); a wiring board ([0053] The display panel driver 120 may drive the display panel 110. To accomplish this, the display panel driver 120 may include a gate driver, a data driver, a sensing driver); and a circuit board that is electrically coupled to the electro- optical device via the wiring board ([0057] The timing controller may generate a plurality of control signals and provide the generated control signals to the gate driver, the data driver, and the sensing driver to control the gate driver, the data driver, and the sensing driver), wherein the electro-optical device includes a driving circuit configured to drive the electro-optical device ([0053] The display panel driver 120 may drive the display panel 110. To accomplish this, the display panel driver 120 may include a gate driver, a data driver, a sensing driver), the circuit board includes a first control circuit configured to control the driving circuit ([0057] The timing controller may generate a plurality of control signals and provide the generated control signals to the gate driver, the data driver, and the sensing driver to control the gate driver, the data driver, and the sensing driver), and the driving circuit includes a measurement circuit ([0063] at least two of the display panel driver 120, the panel temperature determiner 140, and the temperature afterimage compensator 150 may be implemented as one configuration) configured to measure a temperature of the electro-optical device based on an output signal from the temperature detection element in a flyback period of the electro-optical device ([0066] the panel temperature determiner 140 may measure the sensing currents SC flowing through the pixels P during the vertical blank period FV of the one frame 1F). As to claim 4, Bang teaches the display module, wherein the flyback period is included in a vertical scanning period ([0066] the panel temperature determiner 140 may measure the sensing currents SC flowing through the pixels P during the vertical blank period FV of the one frame 1F). As to claim 8, Bang teaches an electronic device comprising the display module according to claim 1 (see display panel, fig. 1). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 2023/0162670) in view of Uchino et al (US 2009/0315813). As to claim 3, Bang does not teach wherein the flyback period is included in a horizontal scanning period. However, Uchino teaches the display module, wherein the flyback period is included in a horizontal scanning period ([0157] More particularly, the WSEN2 pulse width conversion block 94 acquires temperature information of the display panel 70 from the detection section 80 periodically, for example, after every one horizontal period). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bang to teach, wherein the flyback period is included in a horizontal scanning period, as suggested by Uchino. The motivation would have been in order to improve the display quality ([0014]). 3. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 2023/0162670) in view of Ishii (US 2024/0312429). As to claim 5, Bang does not teach the measurement circuit as claimed. However, Ishii teaches the display module, wherein the measurement circuit includes: a constant current source configured to supply a current to the temperature detection element (VCC, fig. 7); an A/D converter configured to convert an output signal from the temperature detection element into a digital value (ADC, fig. 7, [0104]); and a second control circuit configured to control the A/D converter to make the output signal from the temperature detection element taken into the A/D converter in the flyback period ([0104] The gate control part 27 outputs the enable control signal ES of H level (logical level 1) in the blank period BP as a temperature measurement period. Accordingly, the MUX wiring MW is connected to the resistance value measurement part 34C, the resistance value is measured, and the temperature is calculated by the temperature calculator 35C). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bang to teach, the measurement circuit, as suggested by Ishii. The motivation would have been in order to accurately perform temperature correction ([0004]). 4. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 2023/0162670) in view of Wang et al (US 2019/0304374). As to claim 6, Bang does not teach a plurality of demultiplexers as claimed. However, Wang teaches the display module, wherein the electro-optical device includes a signal line driving circuit (data driver 30, fig. 1) including a plurality of demultiplexers (demux unit, fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bang to teach, a plurality of demultiplexers, as suggested by Wang. The motivation would have been in order to prevent current leakage and flicker ([0005]). 5. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 2023/0162670) in view of Fujikawa (US 2021/0104186). As to claim 7, Bang does not teach a diode as claimed. However, Fujikawa teaches the display module, wherein the temperature detection element is a diode ([0032] temperature detection element 13 consists of a diode 130). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bang to teach, wherein the temperature detection element is a diode, as suggested by Fujikawa. The motivation would have been in order to properly monitoring the temperature of the display region ([0005]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMEN W BOGALE/Examiner, Art Unit 2628 /NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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Prosecution Timeline

Mar 26, 2025
Application Filed
Jan 21, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
78%
With Interview (+4.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 455 resolved cases by this examiner. Grant probability derived from career allow rate.

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