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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-12 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-15, 17, and 18 of U.S. Patent No. 11,069,281 (resulting from parent application 16/633,370), in view of Chen (US 2018/0268755).
• Regarding claims 1-12 and 14-20, US 11,069,281 claims everything in claims 1-3, 5-15, 17, and 18, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Chen discloses the additional details of the shift register, as shown in the following table.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 11,069,281 according to the teachings of Chen, for the purpose of at least partially alleviating an electric leakage in a pull-down node of a shift register and the resulting noises of a gate drive signal and a pull-up node (¶ 41).
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9-12 of U.S. Patent No. 11,069,281, in view of Chen, and further in view of Choi (US 2021/0201814).
• Regarding claim 13, US 11,069,281, in view of Chen, claims everything in claims 1 and 9-12, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Choi discloses the additional details of the shift register, as shown in the following table.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 11,069,281, as modified by Chen, according to the teachings of Choi, for the purpose of outputting multiple outputs from a single shift register stage (¶s 170 and 171).
US 19/092,198
US 11,069,281 (16/633,370)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal, and
the second input-output unit comprises a second pull-up node and a second output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the first input-output unit is configured to charge the first pull-up node in response to a first display input signal, and is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the second input-output unit is configured to charge the second pull-up node in response to a second display input signal, and is configured to output the composite output signal to the second output terminal under control of a level of the second pull-up node.
9. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
See claim 11 below
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to the first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
11. The shift register unit according to claim 9, wherein the first input-output unit further comprises
a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
12. The shift register unit according to claim 11, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node; …
2. The shift register unit according to claim 1, wherein
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node; and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor;
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node; and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
At least suggested by the configuration of the blanking pull-up circuit:
2. The shift register unit according to claim 1, wherein…
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node, the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit, …
At least suggested by:
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
…the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal; …
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
6. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, and a first electrode of the first transmission transistor is connected to the blanking pull-up node to receive the blanking pull-up signal, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
7. The shift register unit according to claim 1, wherein
the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive the second transmission signal, a first electrode of the second transmission transistor is connected to the blanking pull-up node to receive the blanking pull-up signal, and a second electrode of the second transmission transistor is connected to the second pull-up node.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
8. The shift register unit according to claim 7, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal,
the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
9. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to the first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
10. The shift register unit according to claim 9, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein the first pull-down auxiliary control circuit comprises
an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
Chen: elements M2 and M3 in figure 10 and ¶s 97 and 98
Chen: note the relationship between element M2 and CLKB in figure 10 and ¶ 97
Chen: note the relationship between elements M2 and M3 and CLKB in figure 10 and ¶s 97 and 98
Chen: note the relationship between PU, VSS, and elements M2, M3, and M5 in figure 10 and ¶ 98
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
Choi: element Cc1 in figure 11
Choi: note the relationship between elements Cc1 and T32 in figure 11
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
11. The shift register unit according to claim 9, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
12. The shift register unit according to claim 11, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 11, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
14. The shift register unit according to claim 9, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
15. The shift register unit according to claim 14, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit, …
the first input-output unit comprises a first pull-up node and a first output terminal, and
the second input-output unit comprises a second pull-up node and a second output terminal; …
the first input-output unit is configured to charge the first pull-up node in response to a first display input signal, and is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the second input-output unit is configured to charge the second pull-up node in response to a second display input signal, and is configured to output the composite output signal to the second output terminal under control of a level of the second pull-up node.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit, the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
18. A display device, comprising
the gate driving circuit according to claim 17 and
a plurality of sub-pixel units arranged in an array,
wherein the first output terminal and the second output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in different rows, respectively.
17. A gate driving circuit, comprising
a plurality of cascaded shift register units according to claim 1.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal, and
the second input-output unit comprises a second pull-up node and a second output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the first input-output unit is configured to charge the first pull-up node in response to a first display input signal, and is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the second input-output unit is configured to charge the second pull-up node in response to a second display input signal, and is configured to output the composite output signal to the second output terminal under control of a level of the second pull-up node.
9. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
See claim 11 below
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to the first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
See claim 18 above
11. The shift register unit according to claim 9, wherein the first input-output unit further comprises
a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
12. The shift register unit according to claim 11, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 8-20 of U.S. Patent No. US 11,403,990 (resulting from parent application 17/355,621), in view of Chen.
• Regarding claims 1-20, US 11,403,990 claims everything in claims 1-6 and 8-20, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Chen discloses the additional details of the shift register, as shown in the following table, for the reasons previously indicated in this Office action.
US 19/092,198
US 11,403,990 (resulting from 17/355,621)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal, and the second input-output unit comprises a second pull-up node and a second output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the first input-output unit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the second input-output unit is configured to output the composite output signal to the second output terminal under control of a level of the second pull-up node.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
1. A shift register unit, comprising …
a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node; …
2. The shift register unit according to claim 1, wherein
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node; and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor;
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node; and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node,
the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit,
see claim 1
wherein the common transmission circuit is electrically connected to the blanking pull-up node;
the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit; and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor, a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
9. The shift register unit according to claim 1, wherein
the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive the second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to the second pull-up node.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
10. The shift register unit according to claim 9, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal,
the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein the first pull-down auxiliary control circuit comprises
an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
Chen: elements M2 and M3 in figure 10 and ¶s 97 and 98
Chen: note the relationship between element M2 and CLKB in figure 10 and ¶ 97
Chen: note the relationship between elements M2 and M3 and CLKB in figure 10 and ¶s 97 and 98
Chen: note the relationship between PU, VSS, and elements M2, M3, and M5 in figure 10 and ¶ 98
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
13. The shift register unit according to claim 12, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
14. The shift register unit according to claim 11, wherein the first input-output unit further comprises
a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
19. The shift register unit according to claim 11, wherein
See claim 1
a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit,
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal, and
the second input-output unit comprises a second pull-up node and a second output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node;
the first input-output unit is configured to charge the first pull-up node in response to a first display input signal, and is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node;
the second input-output unit is configured to charge the second pull-up node in response to a second display input signal, and is configured to output the composite output signal to the second output terminal under control of a level of the second pull-up node; and
the first output terminal and the second output terminal are electrically connected to sub-pixel units in different rows.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
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the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
See claim 20 above
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,942,041 (resulting from parent application 17/838,419). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”).
US 19/092,198
US 11,942,041 (resulting from 17/838,419)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the first input-output unit comprises an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit,
see claim 13 below
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node;
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor,
a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor;
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor; and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
2. The shift register unit according to claim 1, wherein
See below
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node; and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor;
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node; and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node, the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node; the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit; and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal, the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal; the display input circuit is configured to charge the first pull-up node in response to a first display input signal; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor,
a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal; …
1. A shift register unit, comprising …
the first pull-down control circuit comprises a seventh transistor and a ninth transistor,
a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage; …
12. …the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
1. A shift register unit, comprising …
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor;
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor; and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
12. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor, and
a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
13. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
15. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
16. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 16, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
18. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit,
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
19. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit,
see claim 13 below
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node;
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor,
a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor;
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor; and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,293,723 (resulting from parent application 18/444,926). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”).
US 19/092,198
US 12,293,723 (resulting from 18/444,926)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit,
see claim 14 below
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node, and
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node.
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage, and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node, the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node, the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal, the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal, the display input circuit is configured to charge the first pull-up node in response to a first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and
the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
12. The shift register unit according to claim 11, wherein
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal, and …
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor, and …
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage, and …
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit, the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit, the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit,
see claim 14 below
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row.
14. The shift register unit according to claim 11, wherein …
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein …
the third pull-down control circuit comprises a fourteenth transistor, …
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
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Claims 1-12 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 5, 7, and 9-18 of U.S. Patent No. 11,727,853 (resulting from related application 17/842,507), in view of Chen.
• Regarding claims 1-12 and 14-20, US 11,727,853 claims everything in claims 1, 4, 5, 7, and 9-18, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Chen discloses the additional details of the shift register, as shown in the following table, for the reasons previously indicated in this Office action.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 10-13 of U.S. Patent No. 11,727,853, in view of Chen, and further in view of Choi.
• Regarding claim 13, US 11,727,853, in view of Chen, claims everything in claims 1 and 10-13, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Choi discloses the additional details of the shift register, as shown in the following table, for the reasons previously indicated in this Office action.
US 19/092,198
US 11,727,853 (resulting from 17/842,507)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the first input-output unit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node;
the first input-output unit comprises a first leakage preventing structure;
the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node respectively, and
the first leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking;
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node;
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node;
the blanking unit further comprises a blanking leakage preventing structure;
the blanking leakage preventing structure is electrically connected to the pull-up control node and a blanking leakage preventing node respectively; and
the blanking leakage preventing structure is configured to control a level of the blanking leakage preventing node under the control of the level of the pull-up control node to prevent the pull-up control node from leaking.
10. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
see claim 12 below
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
12. The shift register unit according to claim 10, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
13. The shift register unit according to claim 12, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node; …
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node;
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node; …
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 1, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 1, wherein
the blanking input circuit comprises a first transistor, a first pair transistor, and a first capacitor;
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the blanking leakage preventing node;
a gate electrode of the first pair transistor is connected to the compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first pair transistor is connected to the blanking leakage preventing node, and the second electrode of the first transistor is connected to the pull-up control node; and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
7. The shift register unit according to claim 1, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node,
the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
At least suggested by the structure and function of the blanking unit and the first transmission circuit of claim 1 in combination with:
16. The shift register unit according to claim 1, further comprising:
a second transmission circuit and a second input-output unit,
wherein the second input-output unit comprises a second pull-up node and a second output terminal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the second input-output unit is configured to output a composite output signal to the second output terminal under control of a level of the second pull-up node; and
the second input-output unit comprises a second leakage preventing structure,
the second leakage preventing structure is electrically connected to the second pull-up node and a second leakage preventing node respectively, and
the second leakage preventing structure is configured to control a level of the second leakage preventing node under the control of the level of the second pull-up node to prevent the second pull-up node from leaking.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
9. The shift register unit according to claim 8, wherein
the first transmission circuit comprises a first transmission transistor, and a first transmission pair transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first leakage preventing node; and
the gate electrode of the first transmission pair transistor is connected to the first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the first leakage preventing node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
18. The display device according to claim 17, wherein
the shift register unit further comprises a second transmission circuit and a second input-output unit,
wherein the second input-output unit comprises a second pull-up node and a second output terminal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal; …
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
Chen: note the relationship between CLKB and element M2 in figure 10
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal,
the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
10. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
Chen: elements M2 and M3 in figure 10 and ¶s 97 and 98
Chen: note the relationship between element M2 and CLKB in figure 10 and ¶ 97
Chen: note the relationship between elements M2 and M3 and CLKB in figure 10 and ¶s 97 and 98
Chen: note the relationship between PU, VSS, and elements M2, M3, and M5 in figure 10 and ¶ 98
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
Choi: element Cc1 in figure 11
Choi: note the relationship between elements Cc1 and T32 in figure 11
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
12. The shift register unit according to claim 10, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
13. The shift register unit according to claim 12, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
13. The shift register unit according to claim 12, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
14. The shift register unit according to claim 10, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
15. The shift register unit according to claim 14, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
16. The shift register unit according to claim 1, further comprising:
a second transmission circuit and a second input-output unit,
wherein the second input-output unit comprises a second pull-up node and a second output terminal; …
the second input-output unit is configured to output a composite output signal to the second output terminal under control of a level of the second pull-up node; and
the second input-output unit comprises a second leakage preventing structure,
the second leakage preventing structure is electrically connected to the second pull-up node and a second leakage preventing node respectively, and the
second leakage preventing structure is configured to control a level of the second leakage preventing node under the control of the level of the second pull-up node to prevent the second pull-up node from leaking.
1. A shift register unit, comprising …
a blanking unit, a first transmission circuit, and a first input-output unit, …
the first input-output unit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node;
the first input-output unit comprises a first leakage preventing structure;
the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node respectively, and
the first leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking;…
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit,
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
17. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node; …
10. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit; …
see claim 12 below
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and …
Chen: figure 2 and ¶s 65 and 95-98
See claim 18 below
12. The shift register unit according to claim 10, wherein …
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
13. The shift register unit according to claim 12, wherein …
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
18. The display device according to claim 17, wherein …
the first output terminal and the second output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in different rows, respectively.
(remainder of page intentionally left blank)
Claims 1-12 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 6, 8, 9, and 11-18 of U.S. Patent No. 12,014,668 (resulting from related application 18/173,190), in view of Chen.
• Regarding claims 1-12 and 14-20, US 12,014,668 claims everything in claims 1, 3, 6, 8, 9, and 11-18, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Chen discloses the additional details of the shift register, as shown in the following table, for the reasons previously indicated in this Office action.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11-14 of U.S. Patent No. 12,014,668, in view of Chen, and further in view of Choi.
• Regarding claim 13, US 12,014,668, in view of Chen, claims everything in claims 1 and 11-14, as a whole and as shown in the following table, except the additional details of the shift register.
In the same field of endeavor, Choi discloses the additional details of the shift register, as shown in the following table, for the reasons previously indicated in this Office action.
US 19/092,198
US 12,014,668 (resulting from 18/173,190)
1. A shift register unit, comprising
a first transmission circuit and a first input-output unit,
wherein the first input-output unit comprises a first pull-up node and a first output terminal,
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal,
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node, and
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using the blanking pull-up signal, in response to a first transmission signal;
the first input-output unit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the first input-output unit comprises a first leakage preventing structure,
the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node, and
the first leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking,
wherein the first transmission circuit comprises a first transmission transistor, and a first transmission pair transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first leakage preventing node; and
the gate electrode of the first transmission pair transistor is connected to the first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the first leakage preventing node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;
the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
13. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
2. The shift register unit according to claim 1, further comprising
a blanking unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node,
wherein the blanking unit comprises a blanking input circuit and a blanking pull-up circuit,
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node, and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
1. A shift register unit, comprising
a blanking unit, a first transmission circuit and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node; …
3. The shift register unit according to claim 1, wherein
the blanking unit comprises a blanking input circuit and a blanking pull-up circuit;
the blanking input circuit is configured to charge the pull-up control node in response to the compensation selection control signal, and to maintain a level of the pull-up control node; and
the blanking pull-up circuit is configured to input the blanking pull-up signal to the blanking pull-up node under control of the level of the pull-up control node.
3. The shift register unit according to claim 2, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node and is configured to pull-up, by coupling, the level of the pull-up control node.
8. The shift register unit according to claim 3, wherein
the blanking unit further comprises a blanking coupling circuit,
the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to pull-up, by coupling, the level of the pull-up control node.
4. The shift register unit according to claim 2, wherein
the blanking input circuit comprises a first transistor and a first capacitor,
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the pull-up control node, and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
6. The shift register unit according to claim 4, wherein
the blanking input circuit comprises a first transistor, a first pair transistor, and a first capacitor;
a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the blanking leakage preventing node;
a gate electrode of the first pair transistor is connected to the compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first pair transistor is connected to the blanking leakage preventing node, and the second electrode of the first transistor is connected to the pull-up control node; and
a first electrode of the first capacitor is connected to the pull-up control node, and a second electrode of the first capacitor is connected to a first voltage terminal.
5. The shift register unit according to claim 2, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
9. The shift register unit according to claim 3, wherein
the blanking pull-up circuit comprises a second transistor,
a gate electrode of the second transistor is connected to the pull-up control node, a first electrode of the second transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the second transistor is connected to the blanking pull-up node.
6. The shift register unit according to claim 1, further comprising
a common transmission circuit and
a second transmission circuit,
wherein the common transmission circuit is electrically connected to the blanking pull-up node,
the first transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit, and
the second transmission circuit is electrically connected to the blanking pull-up node further through the common transmission circuit.
At least suggested by the structure and function of the blanking unit and the first transmission circuit of claim 1 in combination with:
17. The shift register unit according to claim 1, further comprising:
a second transmission circuit and a second input-output unit,
wherein the second input-output unit comprises a second pull-up node and a second output terminal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the second input-output unit is configured to output a composite output signal to the second output terminal under control of a level of the second pull-up node; and
the second input-output unit comprises a second leakage preventing structure, the second leakage preventing structure is electrically connected to the second pull-up node and a second leakage preventing node, and
the second leakage preventing structure is configured to control a level of the second leakage preventing node under the control of the level of the second pull-up node to prevent the second pull-up node from leaking.
7. The shift register unit according to claim 1, wherein
the first transmission circuit comprises a first transmission transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first pull-up node.
1. A shift register unit, comprising …
wherein the first transmission circuit comprises a first transmission transistor, and a first transmission pair transistor,
a gate electrode of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, a first electrode of the first transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the first transmission transistor is connected to the first leakage preventing node; and …
8. The shift register unit according to claim 1, further comprising
a second transmission circuit,
wherein the second transmission circuit comprises a second transmission transistor,
a gate electrode of the second transmission transistor is connected to a second transmission signal terminal to receive a second transmission signal, a first electrode of the second transmission transistor is electrically connected to the blanking pull-up node, and a second electrode of the second transmission transistor is connected to a second pull-up node.
17. The shift register unit according to claim 1, further comprising:
a second transmission circuit and a second input-output unit,
wherein the second input-output unit comprises a second pull-up node and a second output terminal;
the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to charge the second pull-up node, by using the blanking pull-up signal, in response to a second transmission signal;
the second input-output unit is configured to output a composite output signal to the second output terminal under control of a level of the second pull-up node; and
the second input-output unit comprises a second leakage preventing structure, the second leakage preventing structure is electrically connected to the second pull-up node and a second leakage preventing node, and
the second leakage preventing structure is configured to control a level of the second leakage preventing node under the control of the level of the second pull-up node to prevent the second pull-up node from leaking.
9. The shift register unit according to claim 8, wherein
the second transmission signal terminal comprises a first clock signal terminal, and
the second transmission signal comprises a first clock signal received by the first clock signal terminal.
Chen: note the relationship between CLKB and element M2 in figure 10
10. The shift register unit according to claim 1, wherein
the first input-output unit further comprises a display input circuit and a pull-down circuit,
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal, the display input circuit is configured to charge the first pull-up node in response to the first display input signal, and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit;
the first output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and
the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal; the display input circuit is configured to charge the first pull-up node in response to a first display input signal;
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
11. The shift register unit according to claim 10, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to the display input signal terminal to receive a first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the display input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first pull-up node;
the output circuit comprises a fifth transistor and a sixth transistor,
a gate electrode of the fifth transistor is connected to the first pull-up node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first pull-up node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal;
the first pull-down control circuit comprises a seventh transistor and a ninth transistor, a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is further configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the pull-down node;
a gate electrode of the ninth transistor is connected to the first pull-up node, a first electrode of the ninth transistor is connected to the pull-down node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage;
the pull-down circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor,
a gate electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the fifth voltage terminal to receive the fifth voltage;
a gate electrode of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and
a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
12. The shift register unit according to claim 11, wherein
the first pull-down auxiliary control circuit comprises an auxiliary control switching circuit and an auxiliary control transistor,
a gate electrode of the auxiliary control switching circuit is configured to be connected with the third voltage terminal to receive the third voltage, and
the auxiliary control switching circuit is connected between the third voltage terminal and the gate electrode of the seventh transistor, and
a gate electrode of the auxiliary control transistor is connected to the first pull-up node, a first electrode of the auxiliary control transistor is connected to the gate electrode of the seventh transistor and is connected with the auxiliary control switching circuit, and a second electrode of the auxiliary control transistor is connected to the fifth voltage terminal to receive the fifth voltage.
Chen: elements M2 and M3 in figure 10 and ¶s 97 and 98
Chen: note the relationship between element M2 and CLKB in figure 10 and ¶ 97
Chen: note the relationship between elements M2 and M3 and CLKB in figure 10 and ¶s 97 and 98
Chen: note the relationship between PU, VSS, and elements M2, M3, and M5 in figure 10 and ¶ 98
13. The shift register unit according to claim 11, wherein
the output circuit further comprises a second capacitor,
wherein a second electrode of the second capacitor is connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor.
Choi: element Cc1 in figure 11
Choi: note the relationship between elements Cc1 and T32 in figure 11
14. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit,
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal.
13. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a second pull-down control circuit and a third pull-down control circuit;
the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal; and
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
15. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor,
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and …
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor; …
16. The shift register unit according to claim 14, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to a pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to the display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
14. The shift register unit according to claim 13, wherein
the second pull-down control circuit comprises a thirteenth transistor and a seventeenth transistor, and
the third pull-down control circuit comprises a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;
a gate electrode of the seventeenth transistor is electrically connected to the pull-up control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
17. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
15. The shift register unit according to claim 11, wherein
the first input-output unit further comprises a display reset circuit and a total reset circuit,
the display reset circuit is configured to reset the first pull-up node in response to a display reset signal, and
the total reset circuit is configured to reset the first pull-up node in response to a total reset signal.
18. The shift register unit according to claim 17, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
16. The shift register unit according to claim 15, wherein
the display reset circuit comprises a fifteenth transistor, and
the total reset circuit comprises a sixteenth transistor;
a gate electrode of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, a first electrode of the fifteenth transistor is connected to the first pull-up node, and a second electrode of the fifteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and
a gate electrode of the sixteenth transistor is connected to a total reset signal terminal to receive the total reset signal, a first electrode of the sixteenth transistor is connected to the first pull-up node, and a second electrode of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
19. The shift register unit according to claim 11, further comprising
a second input-output unit,
wherein a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
17. The shift register unit according to claim 1, further comprising:
a second transmission circuit and a second input-output unit, …
Note the similarity between the structure in claims 1 and 17
20. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a first transmission circuit, and a first input-output unit,
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node;
the first input-output unit comprises an output circuit, a first pull-down control circuit, a first pull-down auxiliary control circuit, and a third pull-down control circuit,
wherein the output circuit is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node,
the first pull-down control circuit is configured to control a level of a pull-down node under the control of the level of the first pull-up node,
the first pull-down auxiliary control circuit is configured to control the first pull-down control circuit so as to further control a level of the pull-down node under the control of the level of the first pull-up node; and
the first output terminal of each shift register unit in the gate driving circuit are electrically connected to sub-pixel units in a row,
the third pull-down control circuit is configured to control the level of the pull-down node in response to a first display input signal,
the third pull-down control circuit comprises a fourteenth transistor,
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage.
18. A display device, comprising
a gate driving circuit, and
a plurality of sub-pixel units arranged in an array,
wherein the gate driving circuit comprises a plurality of cascaded shift register units,
each of the plurality of cascaded shift register units comprises a blanking unit, a first transmission circuit, and a first input-output unit,
wherein the blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node;
the first input-output unit comprises a first pull-up node and a first output terminal;
the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node;
the first input-output unit is configured to charge the first pull-up node in response to a first display input signal, and is configured to output a composite output signal to the first output terminal under control of a level of the first pull-up node; and
the first input-output unit comprises a first leakage preventing structure, the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node, and
the first leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking; and
the first output terminal of each shift register unit in the gate driving circuit is electrically connected to a row of sub-pixel units.
11. The shift register unit according to claim 1, wherein
the first input-output unit comprises a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit; …
See claim 13 below
the output circuit is configured to output the composite output signal to the first output terminal under control of the level of the first pull-up node;
the first pull-down control circuit is configured to control a level of a pull-down node under control of the level of the first pull-up node; and
the pull-down circuit is configured to pull down and reset the first pull-up node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the pull-down node.
Chen: figure 2 and ¶s 65 and 95-98
See the last limitation in claim 18 above
13. The shift register unit according to claim 11, wherein …
the third pull-down control circuit is configured to control the level of the pull-down node in response to the first display input signal.
14. The shift register unit according to claim 13, wherein …
the third pull-down control circuit comprises a fourteenth transistor; …
a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, a first electrode of the fourteenth transistor is connected to the pull-down node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the Double Patenting rejections set forth in this Office action, or upon the filing of at least one proper Terminal Disclaimer cumulatively listing every US Patent and US Application forming the basis of the Double Patenting rejections set forth in this Office action. See MPEP §§ 804.02(II) and 804.02(IV).
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest, in claims 1 and 20, where “the first transmission circuit is electrically connected to a blanking pull-up node and the first pull-up node, and is configured to charge the first pull-up node, by using a blanking pull-up signal, in response to a first transmission signal” (as found in claim 1 and similarly found in claim 20), in combination with all the remaining limitations in each claim. Claims 2-19 would be allowable based on their dependence from claim 1.
Closing Remarks/Comments
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622