Notice of Pre-AIA or AIA Status
1. The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
SUMMARY
2. Patent application(CON) filed on March 27, 2025, has been received and made of record. There are 1-20 claims in the application of which claims 1 and 16 are independent claims. Therefore, claims 1-20 are pending for consideration.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on April 01, 2025, was filed after the mailing date of the application on March 27, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-isclaimer.
4. Claims 1-4, 6-8, 13, and 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,287,940 B2 in view of CHEN et al.(US 2017/0017343 A1)(herein after CHEN).
Comparison of claims of the current application and the U.S. published patent No. US 12,287,940 B2 is given below: -
19/092,242
US 12,287,940 B2
Claim 1: A capacitance module, comprising:
a set of electrodes on a first layer in a stack of layers;
a first noise sense electrode electrically shielded from the set of capacitance electrodes;
a second noise sense electrode electrically shielded from the set of capacitance electrodes;
processing resources in electrical communication with the set of capacitance electrodes and the noise sense electrode;
wherein the processing resources include a processor and memory, the memory including programmed instructions that cause the processor, when executed, to:
take a first noise measurement with the first noise electrode;
take a second noise measurement with a second noise electrode; and
determine a capacitance measurement frequency based on the first noise measurement and the second noise measurement.
Claim 1: A capacitance module, comprising:
a set of electrodes;
a noise sense electrode electrically independent from the set of capacitance electrodes;
processing resources in electrical communication with the set of capacitance electrodes and the noise sense electrode;
wherein the processing resources include a processor and memory, the memory including programmed instructions that cause the processor, when executed, to:
take a first noise measurement by imposing a first signal on the noise sense electrode, the first signal having a first frequency;
take a second noise measurement by imposing a second signal on the noise sense electrode, the second noise signal having a second frequency; and
take a capacitance measurement by imposing a third signal on the set of capacitance electrodes, the third signal having a third frequency where the third frequency is the same as the first frequency when the first noise measurement is lower than the second noise measurement or the third frequency is the same as the second frequency when the second noise measurement is lower than the first noise measurement.
The only difference in claims between the published U. S. patent No. US 12,287,940 B2 and the current application is the missing claim limitations, “a second noise sense electrode electrically shielded from the set of capacitance electrodes”.
However, CHEN teaches a noise reduction capacitive touch control panel, comprising:
a set of electrodes(sensing electrodes 30, fig.1, Para-14) on a first layer(top board 14, fig.1) in a stack of layers(10, 12, 14, figs.1-3, and related text);
a first noise sense electrode(noise sensing electrode 40, fig.1, Para-14; also fig.7) electrically shielded(Para-17) from the set of capacitance electrodes(30, fig.1); and
a second noise sense electrode(noise sensing electrode 40, fig.1, Para-14) electrically shielded(Para-17) from the set of capacitance electrodes(30, fig.1; also fig.7).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified the claim of published U. S. patent No. US 12,287,940 B2 with the teaching of CHEN to include the feature in order to provide a touch sensing panel that efficiently reduces environmental noise, 60 Hz noise, and display noise and keeping strength of the touch signal needed.
Claim 2 corresponds to part of claim 1 of US 12,287,940 B2;
Claim 3 corresponds to part of claim 1 of US 12,287,940 B2;
Regarding claim 4, claim of US 12,287,940 B2 as modified by CHEN teaches the capacitance module of claim 3, further including subtracting the noise value from the capacitance measurement to create a processed capacitance measurement (Para-19, CHEN).
Regarding claim 6, claim of US 12,287,940 B2 as modified by CHEN teaches the capacitance module of claim 1, wherein the first noise sense electrode(40) is on the same layer as the set of capacitance electrodes(30, fig.1, CHEN).
Claim 7 corresponds to part of claims 6 and 9 of US 12,287,940 B2;
Claim 8 corresponds to part of claims 6 and 9 of US 12,287,940 B2;
Claim 13 corresponds to part of claim 1 of US 12,287,940 B2;
Claim 15 corresponds to part of claim 8 of US 12,287,940 B2;
Claim 16 is rejected for the same reason as mentioned in the rejection of claim 1;
Claim 17 corresponds to part of claim 1 of US 12,287,940 B2;
Claim 18 corresponds to part of claim 1 of US 12,287,940 B2; and
Claim 19 is rejected for the same reason as mentioned in the rejection of claim 4.
5. Claims 5 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,287,940 B2 in view of CHEN et al.(US 2017/0017343 A1) and further in view of FOTOPOULOS et al.(US 2021/0041988 A1) (herein after FOTOPOULOS).
For mapping and motivation see the rejection of claims 5 and 20 under 35 U.S.C. 103.
6. Claims 9-10 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,287,940 B2 in view of CHEN et al.(US 2017/0017343 A1), and further in view of Katsurahira et al.(US 2016/0378265 A1) (herein after Katsurahira).
For mapping and motivation see the rejection of claims 9-10 and 12 under 35 U.S.C. 103.
7. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,287,940 B2 in view of CHEN et al.(US 2017/0017343 A1), and further in view of SUNG et al.(US 2021/0328328 A1) (herein after SUNG).
For mapping and motivation see the rejection of claim 11 under 35 U.S.C. 103.
8. Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,287,940 B2 in view of CHEN et al.(US 2017/0017343 A1), and further in view of SCHWARTZ(US 2017/0168604 A1).
For mapping and motivation see the rejection of claims 1 and 12 under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
12. Claims 1-4, 6, and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1)(herein after CHEN) in view of SCHWARTZ(US 2017/0168604 A1).
Regarding claim 1, CHEN teaches a capacitance module(noise reduction capacitive touch control panel, figs.1-3, Para-14), comprising:
a set of electrodes(sensing electrodes 30, fig.1, Para-14) on a first layer(top board 14, fig.1; also fig.7 and related text) in a stack of layers(10, 12, 14, figs.1-3, 5-7 and related text);
a first noise sense electrode(noise sensing electrode 40, fig.1, Para-14) electrically shielded(Para-17) from the set of capacitance electrodes(30, fig.1); and
a second noise sense electrode(noise sensing electrode 40, fig.1, Para-14) electrically shielded(Para-17) from the set of capacitance electrodes(30, fig.1);
processing resources(microcontroller 60, fig.2) in electrical communication(Para-19) with the set of capacitance electrodes (20 or 30, figs.1-3) and the noise sense electrode(40, figs.1-3 and related text);
wherein the processing resources(60) include a processor and memory(obvious to have memory or storage device in a microcontroller), the memory including programmed instructions that cause the processor, when executed, to:
take a first noise measurement with the first noise electrode (Para-19: receives noise sensing signals from the noise sensing electrodes 40 through the noise sensing electrode wires 46);
take a second noise measurement with a second noise electrode (Para-19: receives noise sensing signals from the noise sensing electrodes 40 through the noise sensing electrode wires 46); and
Nevertheless, CHEN is not found to teach expressly the capacitance module, wherein the processor is configured to
determine a capacitance measurement frequency based on the first noise measurement and the second noise measurement.
However, SCHWARTZ teaches a capacitive sensing device, wherein the processor is configured to
determine a capacitance measurement frequency based on the first noise measurement and the second noise measurement (figs.3&4 and related text; claim 5).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN with the teaching of SCHWARTZ to include the feature in order to provide a system that improves flexibility to mix and match orthogonal frequencies independently and utilizes specific predefined frequency pairs to avoid interference.
Regarding claim 2, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, further including taking a capacitance noise measurement(Para-19, CHEN) with the determined capacitance measurement(Para-17, CHEN) frequency (Para-61, SCHWARTZ).
Regarding claim 3, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 2, further including determining a noise value(Para-19, CHEN) from the selected capacitance measurement frequency(Para-61, SCHWARTZ).
Regarding claim 4, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 3, further including subtracting the noise value from the capacitance measurement to create a processed capacitance measurement(Para-19, CHEN).
Regarding claim 6, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, wherein the first noise sense electrode is on the same layer as the set of capacitance electrodes(figs.5-7, and related texts, CHEN).
Regarding claim 13, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, wherein the first noise measurement performed at a first frequency that is different than a second frequency of the second noise measurement (figs.3&4, SCHWARTZ).
Regarding claim 14, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, wherein determining the capacitance measurement frequency includes selecting a first frequency of the first noise measurement in response to the first noise measurement obtaining a lower noise value than obtained in the second noise measurement or selecting a second frequency of the second noise measurement in response to the second noise measurement obtaining a lower noise value than the first noise measurement(Para-65: The determination module 220 can apply one or more thresholds to one or more interference metrics to determine an interference environment; fig.4, Para-66, SCHWARTZ).
Regarding claim 15, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, wherein the first noise measurement and second noise measurement are taken at the same time(Para-53, SCHWARTZ).
Claim 16 is rejected for the same reason as mentioned in the rejection of claim 1, since both claims 1 and 16 recite identical claim limitations excepts presented in different formats.
Claim 17 is rejected for the same reason as mentioned in the rejection of claim 2, since both claims 2 and 17 recite identical claim limitations excepts presented in different formats.
Claim 18 is rejected for the same reason as mentioned in the rejection of claim 3, since both claims 3 and 18 recite identical claim limitations excepts presented in different formats.
Claim 19 is rejected for the same reason as mentioned in the rejection of claim 4, since both claims 4 and 19 recite identical claim limitations excepts presented in different formats.
13. Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1) in view of SCHWARTZ(US 2017/0168604 A1) and further in view of FOTOPOULOS et al.(US 2021/0041988 A1) (herein after FOTOPOULOS).
Regarding claim 5, CHEN as modified by SCHWARTZ is not found to teach expressly the capacitance module of claim 4, further including determining a user input when the processed capacitance measurement exceeds a predetermined input threshold value.
However, FOTOPOULOS teaches a system for corrected sensor data further including determining a user input when the processed capacitance measurement exceeds a predetermined input threshold value(Para-81).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of FOTOPOULOS to include the feature in order to provide a touch sensing system that minimizes errors within the reported positional information of the input object or the input object, by averaging absolute capacitive sensor data of a current capacitive frame with that of a previous capacitive frame.
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 5, since both claims 5 and 20 recite identical claim limitations excepts presented in different formats.
14. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1) in view of SCHWARTZ(US 2017/01 68604 A1) and further in view of Yun et al.(US 2022/0317803 A1) (herein after Yun).
Regarding claim 7, CHEN as modified by SCHWARTZ is not found to teach expressly the capacitance module of claim 6, where the first noise sense electrode is shielded from the set of capacitance electrodes with a grounded electrically conductive barrier that is positioned between the first noise sense electrode and the set of capacitance electrodes.
However, Yun teaches a display device having touch sensor, where the first noise sense electrode(NDs_1, fig.11, Para-180) is shielded from the set of capacitance electrodes(SP1 and SP2, figs.4&11)with a grounded electrically conductive barrier (touch ground G4, fig.11, Para-114, 179) that is positioned between the first noise sense electrode(NDs_1) and the set of capacitance electrodes(SP1 and SP2).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of Yun to include the feature in order to provide a touch panel capable of detecting noise caused by poor deposition of a cathode electrode.
15. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1) in view of SCHWARTZ(US 2017/01 68604 A1) and further in view of HA et al.(US 2019/0121396 A1) (herein after HA).
Regarding claim 8, CHEN as modified by SCHWARTZ is not found to teach expressly the capacitance module of claim 1, wherein the stack of layers includes a shield layer that reduces or eliminates electrical interference generated on an underside of the stack of layers from interfering with an operation of the capacitance electrodes.
However, HA teaches an electronic device, wherein the stack of layers(440, fig.4B, Para-101) includes a shield layer (shielding layer 442 or shielding layer 444, fig.4B) that reduces or eliminates electrical interference(Para-103: reduce the noise due to interference between the touch panel or display panel and the antenna) generated on an underside of the stack of layers from interfering with an operation of the capacitance electrodes(touch panel 441, fig.4B, Para-101; Para-68: capacitive technique).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of HA to include the feature in order to provide a touch panel capable of reducing noise due to interference between the touch panel or display panel and the antenna.
16. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1), SCHWARTZ(US 2017/0168604 A1), HA et al.(US 2019/0121396 A1) and further in view of Katsurahira et al.(US 2016/0378265 A1)(herein after Katsurahira).
Regarding claim 9, CHEN as modified by SCHWARTZ and HA is not found to teach expressly the capacitance module of claim 8, wherein the shield layer is between the second noise sense electrode and the set of capacitance sense electrodes.
However, Katsurahira teaches a position detecting device, wherein the shield layer(shield member 43, fig.14, Para-117) is between a noise sense electrode(noise sensor 12C, fig.14) and the set of capacitance sense electrodes(transparent sensor 11, fig.14, Para-116) .
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of Katsurahira to include the feature in order to provide a digitize capable of detecting noise efficiently by making an opening in the shield member.
Regarding claim 10, CHEN as modified by SCHWARTZ and HA is not found to teach expressly the capacitance module of claim 8, wherein the second noise sense electrode is located on an underside layer of the stack of layers
However, Katsurahira teaches a position detection device, wherein a noise sense electrode is located on an underside layer of the stack of layers(fig.14).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of Katsurahira to include the feature in order to provide a digitizer that controls phase of pulse in sync with outputted pulse so that the noise detection information is outputted in predetermined time.
17. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1) in view of SCHWARTZ(US 2017/01 68604 A1) and further in view of SUNG et al.(US 2021/0328328 A1) (herein after SUNG).
Regarding claim 11, CHEN as modified by SCHWARTZ teaches the capacitance module of claim 1, wherein the set of capacitance electrodes(20 and 30, CHEN) and the first noise sense electrode (40) are on the same layer of the stack of layers(12, 14, figs.1-7, CHEN).
Neither CHEN nor SCHWARTZ teaches expressly the capacitance module, where stack of layers includes an antenna and it is on the same layer as the set of the capacitance electrodes.
However, SUNG teaches wireless electronic device, wherein the antenna and the set of the capacitance electrodes places on the same layer(Para-96).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of SUNG to include the feature in order to provide an electronic device having an improved antenna efficiency by arranging a dipole antenna in a display area using a portion of an input sensor panel.
18. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al.(US 2017/0017343 A1) in view of SCHWARTZ(US 2017/01 68604 A1) and further in view of Katsurahira et al.(US 2016/0378265 A1)(herein after Katsurahira).
Regarding claim 12, CHEN as modified by SCHWARTZ is not found to teach expressly the capacitance module of claim 1, wherein the stack of layers includes an antenna and is on an underside layer, and the second noise sense electrode is also on the underside layer
However, Katsurahira teaches a position detection device, wherein the stack of layers includes an antenna(coil pattern 112, fig.15A) and is on an underside layer(fig.14), and a noise sense electrode(12C) is also on the underside layer(figs.14-15B).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified CHEN further with the teaching of Katsurahira to include the feature in order to provide a digitizer capable of not only blocking noise but also blocking heat generated in the display panel that affecting circuit part of portable device.
Examiner Note
19. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
CONTACT
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2621