DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 4-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12315033 and 10726520. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-19 of U.S. Patent No. 12315033 and 10726520 has a narrower scope than the instant application.
Claims 2-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12315033 and claim 8 of U.S. Patent No. 10726520. The claims 8 and 10, from the US patents, teaches the use a register. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize a register to store and to retrieve preference data value. It is well known in the art to that read/write data value for a register is fast with low latency as it is located directly on the computing units. It is designer’s preference to achieve faster processing time. The results of the combination would have been predictable.
Instant Application
Patent No. 12315033
Patent No. 10726520
1. A system for controlling processing of commands submitted for processing at a graphics processor, to cause the graphics processor to write at least one buffer of data to an external memory, the system comprising a driver operable to communicate with the graphics processor;
the system being configured to access data related to a command submitted for processing at the graphics processor, the accessed data indicating whether a buffer of data is to be written to external memory, and to determine in dependence on the accessed data that the buffer of data does not need to be written to external memory,
the system being configured to access the data related to the command during an operation to write the buffer of data to external memory; and
the driver being configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
2. The system according to claim 1, wherein the system further comprises a control register configured to store a value associated with the command.
3. The system according to claim 2, wherein the system is configured to check the value stored at the control register during the operation to write the buffer of data to external memory.
4. The system according to claim 1, wherein the system is configured to periodically access the data related to the command whilst the operation is occurring.
5. The system according to claim 1, wherein the system is configured to access the data related to the command where it is determined that: the operation will take longer than a threshold length of time, and/or the operation will take longer than a threshold number of clock cycles, and/or the operation relates to an amount of data greater than a threshold amount of data.
6. The system according to claim 1, in which the system further comprises rendering logic, and the rendering logic is configured to access the data related to the command.
7. The system according to claim 1, in which the write to external memory occurs in multiple stages or blocks.
8. The system according to claim 1, wherein the system is configured to determine that the buffer of data does not need to be written to external memory by being configured to determine that subsequent commands will not use the buffer of data stored at the external memory.
9. The system according to claim 8, wherein the system is configured to determine that subsequent commands will not use the buffer of data stored at the external memory by being configured to determine that input data received at the system does not request access to the buffer of data prior to the buffer of data being cleared or invalidated.
10. The system according to claim 9, wherein the system further comprises a data structure, and the system is configured to determine that the input data does not request access to the buffer of data prior to the buffer of data being cleared or invalidated by being configured to:
maintain the data structure to track access requests to the buffer of data received in the input data; and
analyse the data structure when a function to clear or invalidate the buffer of data is received to determine whether a prior access request was made.
11. The system according to claim 1, wherein the command comprises at least one configuration register setting that will cause the graphics processor to write the at least one buffer of data to the external memory.
12. The system according to claim 1, wherein the driver is configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command by being configured to one or more of:
signal to a queue, to which the command is submitted for later processing at the graphics processor, to modify the command held in the queue, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory;
signal to the graphics processor to modify the command prior to being processed, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory;
signal to the graphics processor to modify the command while the command is being processed, such that the command will not cause the graphics processor to write out at least a portion of the at least one buffer of data to the external memory; and
generate an interrupt signal to cause the graphics processor to stop processing the command.
13. The system according to claim 12, further comprising a command processor, wherein the command processor is configured, responsive to the signal, to store an identifier for the command and at least one buffer of data and modify the command responsive to determining that the command received for processing has a matching identifier.
14. The system according to claim 1, wherein the command comprises a pointer to a location in the external memory which comprises set-up data that will cause the graphics processor to write the at least one buffer of data to the external memory.
15. The system according to claim 1, wherein the command comprises at least one pointer to graphics data stored in the external memory.
16. The system according to claim 1, wherein the command submitted for processing is submitted to a queue for later processing at the graphics processor, and wherein the queue is a command queue configured to store commands at the graphics processor until they can be processed at the graphics processor.
17. The system according to claim 1, wherein the driver is further configured to receive initial input data and generate the command for processing at the graphics processor from the initial input data, the initial input data comprising a plurality of application programming interface function calls.
18. The system according to claim 1, wherein input data received at the system comprises a plurality of application programming interface function calls comprising at least one of:
a clear function configured to cause the buffer of data stored in the external memory to be cleared; and
an invalidate function configured to cause the buffer of data stored in the external memory to be invalidated.
19. A method for controlling processing of commands submitted for processing at a graphics processor, to cause the graphics processor to write at least one buffer of data to an external memory, the method comprising:
during an operation to write a buffer of data to external memory, accessing data related to a command submitted for processing at the graphics processor, the accessed data indicating whether the buffer of data is to be written to external memory;
determining in dependence on the accessed data that the buffer of data does not need to be written to external memory; and
signalling to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
20. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to control processing of commands submitted for processing at a graphics processor, to cause the graphics processor to write out at least one buffer of data to an external memory, the computer system being caused to
during an operation to write a buffer of data to external memory, access data related to a command submitted for processing at the graphics processor, the accessed data indicating whether the buffer of data is to be written to external memory;
determine in dependence on the accessed data that the buffer of data does not need to be written to external memory; and
signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
1. A system for controlling processing of commands submitted in a queue for processing at a graphics processor, to cause the graphics processor to write at least one buffer of data to an external memory, the system comprising a driver operable to communicate with the graphics processor,
the system being configured to access data related to a command of said submitted commands for processing at the graphics processor, the accessed data indicating whether a buffer of data is to be written to external memory, and to determine in dependence on the accessed data that the buffer of data does not need to be written to external memory by being configured to determine whether there is one or both of an implicit invalidation of the data and an explicit invalidation of the data; and
the driver being configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
2. The system according to claim 1, wherein the system is configured to access the data related to the command during an operation to write the buffer of data to external memory.
10. The system according to claim 1, wherein the command comprises at least one configuration register setting that will cause the graphics processor to write the at least one buffer of data to the external memory.
3. The system according to claim 2, wherein the system is configured to periodically access the data related to the command whilst the operation is occurring.
4. The system according to claim 2, wherein the system is configured to access the data related to the command where it is determined that: the operation will take longer than a threshold length of time, and/or the operation will take longer than a threshold number of clock cycles, and/or the operation relates to an amount of data greater than a threshold amount of data.
5. The system according to claim 1, in which the system further comprises rendering logic, and the rendering logic is configured to access the data related to the command.
6. The system according to claim 1, in which the write to external memory occurs in multiple stages or blocks.
7. The system according to claim 1, wherein the system is configured to determine that the buffer of data does not need to be written to external memory by being configured to determine that subsequent commands will not use the buffer of data stored at the external memory.
8. The system according to claim 7, wherein the system is configured to determine that subsequent commands will not use the buffer of data stored at the external memory by being configured to determine that input data received at the system does not request access to the buffer of data prior to the buffer of data being cleared or invalidated.
9. The system according to claim 8, wherein the system further comprises a data structure, and the system is configured to determine that the input data does not request access to the buffer of data prior to the buffer of data being cleared or invalidated by being configured to:
maintain the data structure to track access requests to the buffer of data received in the input data; and
analyse the data structure when a function to clear or invalidate the buffer of data is received to determine whether a prior access request was made.
10. The system according to claim 1, wherein the command comprises at least one configuration register setting that will cause the graphics processor to write the at least one buffer of data to the external memory.
11. The system according to claim 1, wherein the driver is configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command by being configured to one or more of:
signal to said queue, to which the command is submitted for later processing at the graphics processor, to modify the command held in the queue, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory,
signal to the graphics processor to modify the command prior to being processed, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory,
signal to the graphics processor to modify the command while the command is being processed, such that the command will not cause the graphics processor to write out at least a portion of the at least one buffer of data to the external memory, and
generate an interrupt signal to cause the graphics processor to stop processing the command.
12. The system according to claim 11, further comprising a command processor, wherein the command processor is configured, responsive to the signal, to store an identifier for the command and at least one buffer of data and modify the command responsive to determining that the command received for processing has a matching identifier.
13. The system according to claim 1, wherein the command comprises a pointer to a location in the external memory which comprises set-up data that will cause the graphics processor to write the at least one buffer of data to the external memory.
14. The system according to claim 1, wherein the command comprises at least one pointer to graphics data stored in the external memory.
15. The system according to claim 1, wherein the command submitted for processing is submitted to said queue for later processing at the graphics processor, and wherein the queue is a command queue configured to store commands at the graphics processor until they can be processed at the graphics processor.
16. The system according to claim 1, wherein the driver is further configured to receive initial input data and generate the command for processing at the graphics processor from the initial input data, the initial input data comprising a plurality of application programming interface function calls.
17. The system according to claim 1, wherein input data received at the system comprises a plurality of application programming interface function calls comprising at least one of:
a clear function configured to cause the buffer of data stored in the external memory to be cleared; and
an invalidate function configured to cause the buffer of data stored in the external memory to be invalidated.
18. A method for controlling processing of commands submitted in a queue for processing at a graphics processor, to cause the graphics processor to write at least one buffer of data to an external memory, the method comprising:
accessing data related to a command of said submitted commands for processing at the graphics processor, the accessed data indicating whether a buffer of data is to be written to external memory;
determining in dependence on the accessed data that the buffer of data does not need to be written to external memory by determining whether there is one or both of an implicit invalidation of the data and an explicit invalidation of the data; and
signalling to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
19. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to control processing of commands submitted in a queue for processing at a graphics processor, to cause the graphics processor to write out at least one buffer of data to an external memory, the computer system being caused to
access data related to a command of said submitted commands for processing at the graphics processor, the accessed data indicating whether a buffer of data is to be written to external memory;
determine in dependence on the accessed data that the buffer of data does not need to be written to external memory by determining whether there is one or both of an implicit invalidation of the data and an explicit invalidation of the data; and
signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command..
1. A system for controlling processing of commands at a graphics processor, the system comprising a driver operable to communicate with the graphics processor, the driver being configured to:
receive input data and generate a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory;
submit the command to a queue for later processing at the graphics processor;
receive further input data and determine in dependence on the further input data that the buffer of data does not need to be written to external memory; and
signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
2. The system according to claim 1, wherein the driver is configured to determine that the buffer of data does not need to be written to external memory by being configured to determine that subsequent commands will not use the buffer of data stored at the external memory.
3. The system according to claim 2, wherein the driver is configured to determine that subsequent commands will not use the buffer of data stored at the external memory by being configured to determine that the further input data does not request access to the buffer of data prior to the buffer of data being cleared or invalidated.
4. The system according to claim 3, wherein the driver further comprises a data structure, and the driver is configured to determine that the further input data does not request access to the buffer of data prior to the buffer of data being cleared or invalidated by being configured to:
maintain the data structure to track access requests to the buffer of data received in the further input data; and
analyse the data structure when a function to clear or invalidate the buffer of data is received to determine whether a prior access request was made.
5. The system according to claim 4, wherein the data structure comprises an identifier identifying the buffer of data and the command against a flag indicating whether an access request has been received.
6. The system according to claim 4, wherein the driver is configured to one or more of:
maintain the data structure to track access requests by determining whether an application-level or driver-level access request is received for the buffer of data, and
track accesses to the buffer of data to be written at an application or driver layer in system hierarchy to determine that there is no access request.
7. The system according to claim 1, wherein the driver is configured to determine that the buffer of data does not need to be written to external memory by being configured to determine whether there is one or both of an implicit invalidation of the data and an explicit invalidation of the data.
8. The system according to claim 1, wherein the command comprises at least one configuration register setting that will cause the graphics processor to write out the at least one buffer of data to the external memory.
9. The system according to claim 1, wherein the driver is configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command by being configured to one or more of:
signal to the queue to modify the command held in the queue, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory,
signal to the graphics processor to modify the command prior to being processed, such that the command will not cause the graphics processor to write out at least one buffer of data to the external memory,
signal to the graphics processor to modify the command while the command is being processed, such that the command will not cause the graphics processor to write out at least a portion of the at least one buffer of data to the external memory, and
generate an interrupt signal to cause the graphics processor to stop processing the command.
10. The system according to claim 9, further comprising a command processor, wherein the command processor is configured, responsive to the signal, to store an identifier for the command and at least one buffer of data and modify the command responsive to determining that the command received from the queue to be processed has a matching identifier.
11. The system according to claim 1, wherein the command comprises a pointer to a location in the external memory which comprises set-up data that will cause the graphics processor to write out the at least one buffer of data to the external memory.
12. The system according to claim 11, wherein the driver is configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command by modifying the set-up data.
13. The system according to claim 1, wherein the command comprises at least one pointer to graphics data stored in the external memory.
14. The system according to claim 1, wherein the queue is a command queue configured to store commands at the graphics processor until they can be processed at the graphics processor.
15. The system according to claim 1, wherein the driver is configured to operate at a higher level in a system hierarchy than the level at which the command is processed.
16. The system according to claim 1, wherein the input data comprises a plurality of application programming interface function calls.
17. The system according to claim 1, wherein the further input data comprises a plurality of application programming interface function calls comprising at least one of:
a clear function configured to cause the buffer of data stored in the external memory to be cleared; and
an invalidate function configured to cause the buffer of data stored in the external memory to be invalidated.
18. A system according to claim 1, wherein a task to be executed comprises the write of the data buffer and at least one other operation, wherein the driver is configured to prevent at least a portion of the write to external memory from being performed for the command by preventing the graphics processor from completing the execution of the at least one other operation.
19. A method for controlling processing of commands at a graphics processor comprising:
receiving input data and generating a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory;
submitting the command to a queue for later processing at the graphics processor;
subsequent to submitting the command, but before the write to external memory has been completed, receiving further input data and determining in dependence on the further input data that the buffer of data does not need to be written to external memory; and
signalling to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
20. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to:
receive input data and generate a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory;
submit the command to a queue for later processing at the graphics processor;
subsequent to submitting the command, but before the write to external memory has been completed, receive further input data and determine in dependence on the further input data that the buffer of data does not need to be written to external memory; and
signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
The closet prior art regarding the independent claims:
DeLaurier (US 20180181491) teaches:
A system or method… for controlling processing of commands submitted for processing at a graphics processor, to cause the graphics processor to write at least one buffer of data to an external memory, the system comprising a driver operable to communicate with the graphics processor; (DeLaurier at least in Abstract, teaches graphics processing unit includes a cache and one or more storage elements configured to store a plurality of command buffers that include instructions executable to manipulate data stored in the cache.)
the system being configured to access data related to a command submitted for processing at the graphics processor, the accessed data indicating whether a buffer of data is to be written to external memory (DeLaurier at least in par. [0053], L2 cache 110 receives a request to invalidate lines 320 in the cache based on a command buffer ID. In some embodiments, L2 cache 110 invalidates lines 320 without being instructed by other circuitry. L2 cache 110 may invalidate lines 320 without flushing them to memory. For example, if a particular line 320 does not store dirty data as indicated by corresponding flags 335, then L2 cache 110 may invalidate the particular line 320 without flushing it. As such, the methods disclosed for flushing and/or invalidating lines in a cache may be used to only invalidate lines in a cache.), and to determine in dependence on the accessed data that the buffer of data does not need to be written to external memory and the graphics processor to prevent at least a portion of the write to external memory from being performed for the command. (DeLaurier at least in par. [0053], L2 cache 110 receives a request to invalidate lines 320 in the cache based on a command buffer ID. In some embodiments, L2 cache 110 invalidates lines 320 without being instructed by other circuitry. L2 cache 110 may invalidate lines 320 without flushing them to memory. For example, if a particular line 320 does not store dirty data as indicated by corresponding flags 335, then L2 cache 110 may invalidate the particular line 320 without flushing it. As such, the methods disclosed for flushing and/or invalidating lines in a cache may be used to only invalidate lines in a cache.)
DeLaurier is silent to teach the driver being configured to signal to the graphics processor to prevent at least a portion of the write to external memory from being performed for the command.
On the other hand, Chrobak (US 20180095677) teaches the driver being configured to signal to the processor to prevent at least a portion of the write to external memory from being performed for the command. (Chrobak at least in Abstract and par. [0119], teaches the writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped. Chrobak in par. [0233], If either of these conditions is met, then the writing of the output surface as a whole to the external memory is terminated (step 94). This has the effect of terminating the writing of an output frame to external memory where, for example, the number of corrupted lines in the output frame will be too great (greater than a selected limit), or, in the present embodiment, where the first line of the output surface is corrupted (was subject to overrun). Chrobak in par. [0206], The display controller 30 also includes a data flow control module 65 that is operable to direct the data flows through the display controller, i.e. to provide the input layers, composited output surfaces, etc., to the appropriate units for processing as shown in FIG. 6. In the present embodiment, the data flow controller 65 operates under appropriate software control, e.g., and in an embodiment, from a driver for the display controller that is running on a host processor (e.g. the CPU 7) of the overall data processing system that the display controller 30 is part of. The driver may generate appropriate commands for the data flow controller 65 and program control registers of the display controller 30 in response to, e.g., commands and data for display processing received from an application running on the host processor.)
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to implement a system that has a driver to signal to the processor to control data writing to memory, as disclosed by Chrobak, with DeLaurier’s display system. As noticed above, the prior art included each element claimed, although not necessarily in a single prior art reference with the only difference being the lack of actual combination of the elements in a single prior art reference. The examiner finds that one of ordinary skill in the art could combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. Since it was known in the art for a CPU, GPU to contain a driver for controlling data writing to external memory. The results of the combination were predictable.
Conclusion
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/PHUC N DOAN/Examiner, Art Unit 2618
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