Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/27/2025 and 02/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 03/27/2025. These drawings are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11, 13-18, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kanigicherla et al. (US Pat No. 9430432 B2, hereinafter referred to as Kanigicherla) view of Garg et al. (USPGPUB No. 2022/0100247 A1, hereinafter referred to as Garg).
Referring to claim 1, Kanigicherla discloses an apparatus, comprising {“multi-host computing system 100 implementing an optimized MRIOV aware switch 102”, see Fig. 1, Col 7, lines 20-21}:
bridge circuitry configured to bridge {“virtual switch bridge tables' entries of the received port” (see Fig. 1, Col 10, lines 63-65) supported by bridge circuitry “MRIOV core switching module 112” (see Fig. 1, Col 10, lines 25-30)} between a memory system interconnect {“[first memory system] module 204 connected to the DLL module 114 and the MRIOV core switching module 112” (see Figs. 3 and 4, Col 12, lines 56-58) and a second memory system interconnect “OB manager 402, to be able to communicate with both the DLL module and the MRIOV core switching module 112” (see Fig. 4, Col 13, lines 29-32)} and a port controller {“Media Access Controller 118” within each “port 110-1 … port 110-n” (see Fig. 1, Col 9, lines 42-44)}, the port controller for communicating via an external communication link {external link “power control module 212”, see Fig. 5, Col 11, lines 60-62} with a link partner {“DLL packet is received from the link partner” (see Fig. 5, Col 11, lines 60-65)}, the bridge circuitry comprising an internal communication link interface {internal communication link interface “routing mechanism and arbitration”, see Fig. 5, Col 11, lines 16-19} configured to transmit packets via an internal communication link to the port controller {“the MRIOV core switching module 112 includes [transmitting via either] an upstream arbiter 502 and a downstream arbiter 504.”, see Fig. 5, Col 13, lines 63-65};
Kanigicherla does not appear to explicitly disclose wherein in a first state of the bridge circuitry, the bridge circuitry is configured to control the internal communication link interface to transmit a given type of packet to the port controller using a first type of credit;
and in a second state of the bridge circuitry, the bridge circuitry is configured to control the internal communication link interface to transmit the given type of packet to the port controller without using the first type of credit;
wherein the first type of credit represents availability of buffer storage at the link partner.
However, Garg discloses wherein in a first state {dies/interconnect associated with EMIB among them “IO Die-0 1104_1 (e.g., 104) is assumed to be the supervisor power management Die with supervisor p-unit 1102” ([0167], 1st sentence) that indicates/detects first state “guarantees that HPM messages will make forward progress” (see Fig. 3, [0107], 2nd sentence)} of the bridge circuitry {“each die communicates with the other die via an interconnect bridge. One example of the interconnect bridge is EMIB (embedded multi-die interconnect bridge)”, see Figs. 10 and 11, [0166], 1st sentence}, the bridge circuitry is configured to control the internal communication link interface {“[internal communication] P2P fabric supports a credit exchange flow to enable support for PMUs in APs”, see Fig. 3, [0107], last sentence} to transmit a given type of packet to the port controller {“peer-to-peer (P2P) fabric(s) are provided between the various instances of APs allow to for communication between APs (e.g., communication between APs 313 of each supervisee 302”, see Fig. 3, [0104], 1st sentence} using a first type of credit {credit type “P2P fabric supports a credit exchange flow”, see Fig. 3, [0107], last sentence};
and in a second state of the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences}, the bridge circuitry is configured to control the internal communication link interface {“functional HPM architecture 300 with [internal communication links per] two communication fabrics 210 and 211 between supervisor p-unit 302”, see Fig. 3, [0103], 1st sentence} to transmit the given type of packet to the port controller {“supervisor p-unit 202 includes supervisor common interface 223”, see Fig. 2, [0100], 1st sentence; such p-unit includes “compute die p-unit has two ports (RX_DATA, TX_ENB) on one end and another port” (see Fig. 10, 3rd sentence)} without using the first type of credit {essentially each of “supervisee 302” having a respective type of credit in establishing packets between the port controller “supervisor p-unit 202” and “[packets] data-handling functionals units from different physical dielets may be grouped as part of the same fabric domain” (see Figs. 20 and 21, [0250])};
wherein the first type of credit {“dielet 2101-2 then [credit] backflow control circuitry in the fabric I/C ”, see Fig. 21, [0251], last sentence} represents availability of buffer storage at the link partner {“control a data flow rate of the transmission and will buffer data pending [availability] transmission”, see Fig. 21, [0251], last sentence}.
Kanigicherla and Garg are analogous because they are from the same field of endeavor, cloud service provider management.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kanigicherla and Garg before him or her, to modify Kanigicherla’s “ multi-host computing system 100 implementing an optimized MRIOV aware switch 102” (see Fig. 1, Col 7, lines 20-21) incorporating Garg’s “EMIB”/“IO Die-0 1104_1 (e.g., 104)” along with “supervisor p-unit 1102” ([0167], 1st sentence) sending “guarantees that HPM messages will make forward progress” (see Fig. 3, [0107]).
The suggestion/motivation for doing so would have been to implement Hierarchical Power Management serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice mechanism (Garg Abstract, last two sentences) while addressing power and thermal management challenges around enabling large SoCs (Garg [0003]).
Therefore, it would have been obvious to combine Garg with Kanigicherla to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Garg discloses wherein the bridge circuitry is configured to receive a credit exchange message {“ the P2P fabric supports a credit exchange flow”, see Fig. 3, [0107], last sentence } from the port controller indicating availability of the first type of credit {“have limited amount of buffering available to sink HPM commands”, see Fig. 3, [0107], last sentence}.
As per claim 3, the rejection of claim 1 is incorporated and Garg discloses wherein in the first state the bridge circuitry is configured to prohibit the internal communication link interface {“functional HPM architecture 300 with [internal communication links per] two communication fabrics 210 and 211 between supervisor p-unit 302”, see Fig. 3, [0103], 1st sentence} from transmitting the given type of packet to the port controller {“a dynamic back-pressuring throttling mechanism is implemented according to some embodiments to [prohibit] control traffic going from a faster fabric domain into a slower fabric domain”, see Fig. 21, [0254], last two sentences} when there is no availability of the first type of credit {“a [no availability] traffic bottleneck in a slow fabric domain by transmitting too much traffic into it too rapidly from a faster fabric domain”, see Fig. 21, [0254], 2nd sentence}.
As per claim 4, the rejection of claim 1 is incorporated and Garg discloses wherein in the second state of the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences}, the bridge circuitry is responsive to the given type of packet being a first type of packet {“packets [of a first type] may be first routed vertically from a source component”, see Fig. 19, [0234]} to transmit the first type of packet using a second type of credit {“to a destination component at a different location on the fabric and then may be routed horizontally [on a different credit type]”, see Fig. 19, [0234] last two sentences} representing availability of buffer storage at the port controller {“control a data flow rate of the transmission and will buffer data pending [availability] transmission”, see Fig. 21, [0251], last sentence}.
As per claim 5, the rejection of claim 4 is incorporated and Garg discloses wherein the first type of packet requests a completion response {“At 5270, if all buckets have been processed as described in operations 5264-5268, then the process ends at 527”, see Figs. 52a, 52b, [0524] 3rd sentence}.
As per claim 6, the rejection of claim 4 is incorporated and Garg discloses wherein the bridge circuitry is configured to manage an available number {“determines workload activity of its die based on telemetry data and heuristics… the telemetry data includes change in value of one or more hardware performance counters [managed/monitored]”, see Figs. 16, 17a, [0214], 1st sentence} of the second type of credit {“to a destination component at a different location on the fabric and then may be routed horizontally [on a different credit type]”, see Fig. 19, [0234] last two sentences} independent of credit exchange messages from the port controller {“two modes are available for independent fabric control of the data processing apparatus”, see Fig. 30, [0295], last two sentences}.
As per claim 7, the rejection of claim 6 is incorporated and Garg discloses wherein the bridge circuitry is configured to increment an available number {“same globally and based on performance counters and constraints from data-handling functional units”, see Fig. 15, [0210] 2nd sentence} of the second type of credit {“to a destination component at a different location on the fabric and then may be routed horizontally [on a different credit type]”, see Fig. 19, [0234] last two sentences} in response to receipt of a completion packet from the port controller {“At 5270, if all buckets have been processed as described in operations 5264-5268, then the process ends at 527”, see Figs. 52a, 52b, [0524] 3rd sentence}.
As per claim 8, the rejection of claim 4 is incorporated and Garg discloses wherein in the first state of the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences}, the bridge circuitry is configured to control the internal communication link interface {“[internal communication] P2P fabric supports a credit exchange flow to enable support for PMUs in APs”, see Fig. 3, [0107], last sentence} to transmit a packet targeting the port controller {“a dynamic back-pressuring throttling mechanism is implemented according to some embodiments to [prohibit] control traffic going from a faster fabric domain into a slower fabric domain”, see Fig. 21, [0254], last two sentences} via the internal communication link using the second type of credit {“to a destination component at a different location on the fabric and then may be routed horizontally [on a different credit type]”, see Fig. 19, [0234] last two sentences}.
As per claim 9, the rejection of claim 1 is incorporated and Garg discloses wherein in the second state of the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences}, the bridge circuitry is responsive to the given type of packet {“to a destination component at a different location on the fabric and then may be routed horizontally [on a different credit type]”, see Fig. 19, [0234] last two sentences} being a second type of packet {“interconnect fabric having two or more different domains”, each domain having a packet type, which does not distinguish that the second type from the first packet type, see Figs. 23 and 24, [0269] , 1st sentence} to transmit the second type of packet without using any credits {“will buffer data pending transmission by recirculating the data in the fabric of fifth dielet 2101-4 preventing data loss”, see Fig. 21, [0251] last sentence}.
As per claim 11, the rejection of claim 1 is incorporated and Garg discloses wherein in a third state of the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences}, the bridge circuitry is configured to prohibit the internal communication link interface {“functional HPM architecture 300 with [internal communication links per] two communication fabrics 210 and 211 between supervisor p-unit 302”, see Fig. 3, [0103], 1st sentence} from transmitting the given type of packet via the internal communication link {“a dynamic back-pressuring throttling mechanism is implemented according to some embodiments to [prohibit] control traffic going from a faster fabric domain into a slower fabric domain”, see Fig. 21, [0254], last two sentences}.
Referring to claims 13-18 are apparatus claims reciting claim functionality corresponding to the apparatus claim of claims 1-9, and 11, however taken from the perspective/status/state of the port controller, are thereby rejected under the same rationale as claims 1-9, and 11, recited above, inter alia, per claim 18, Garg discloses wherein the port controller is configured to transmit a particular type of packet {“packets [of a particular type] may be first routed vertically from a source component” (see Fig. 19, [0234]), “contribution of global limit f.sub.rc supplied from supervisor p-unit 2602” as a source component/port controller } to the link partner {“control a data flow rate of the transmission and will buffer data pending [availability] transmission”, see Fig. 21, [0251], last sentence} using a reserved type of credit {“a [credit reservation] dynamic back-pressuring throttling mechanism is implemented according to some embodiments to [prohibit] control traffic”, see Fig. 21, [0254], last two sentences}}, the reserved type of credit corresponding to a difference {“Control parameters of the throttling mechanism determined depending on a magnitude of a frequency difference between the two fabric domains”, see Fig. 21, [0254], last sentence} between an availability of buffer storage at the link partner {“have limited amount of buffering available to sink HPM commands”, see Fig. 3, [0107], last sentence} indicated to the bridge circuitry {“These supervisee p-units 303 communicate with the [bridge circuitry] supervisor p-unit 302 to participate in the [plurality of] package level flow[(s)]”, see Fig. 3, [0103], last three sentences} and an availability of buffer storage indicated to the port controller by the link partner {“control a data flow rate of the transmission and will buffer data pending [availability] transmission”, see Fig. 21, [0251], last sentence}.
As per claim 23, the rejection of claim 1 is incorporated and Garg discloses a non-transitory computer-readable storage medium storing computer-readable code for fabrication {“manufacturer, during the fabrication and testing of packaged device 4600”, [0463], 2nd sentence} of the apparatus claim of claim 1 {“The machine-readable medium (e.g., memory 5530) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs”, see Fig. 55, [0562]}.
Referring to claim 24 is a method claim reciting claim functionality corresponding to the apparatus claim of claim 13, however taken from the perspective/status/state of the port controller, are thereby rejected under the same rationale as claim 13.
Referring to claim 25 is a method claim reciting claim functionality corresponding to the apparatus claim of claim 13, however taken from the perspective/status/state of the port controller, are thereby rejected under the same rationale as claim 13.
As per claim 26, the rejection of claim 13 is incorporated and Garg discloses a non-transitory computer-readable storage medium storing computer-readable code for fabrication {“manufacturer, during the fabrication and testing of packaged device 4600”, [0463], 2nd sentence} of the apparatus claim of claim 13 {“The machine-readable medium (e.g., memory 5530) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs”, see Fig. 55, [0562]}.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “bridge circuit”, “memory system”, or “communication link interface”: US 11385939 B2, US 11989586 B1, US 12602345 B2, US 20150222533 A1, US 20180239685 A1, US 20190394096 A1, US 11334382 B2, US 20210216489 A1, US 20210365289 A1, and US 9965331 B2.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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