DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Blaser, US Patent Publication 2019/0305823 in view of Liu, US Patent Publication 2016/0345627.
Regarding independent claim 1, Blaser teaches a method for data transmission by pulling a power line down to a ground line (paragraph 0053 explains that “the power and data circuit 504 modulates the output voltage to encode data within the output power signal. This can be achieved by toggling the output voltage between Vd and ground at a given data rate (e.g., 2K bits per second)”), comprising the following steps: demodulating a waveform signal on a power supply VCC to obtain a demodulated signal (paragraph 0061 explains that “when receiving data, the signal/current demodulation receive circuit 900 can read and demodulate the current draw on power bus 910”); decoding the demodulated signal according to a clock signal to obtain a decoded signal (paragraph 0061 goes on to explain that “the processor can then decode this demodulated current draw to extract the relevant data”); and obtaining a control command according to the decoded signal and an address of an element, wherein the control command is configured to control the element (paragraph 0056 explains that the data includes identifiers and different types of command requests to be sent by the product display assembly 102 to the hardware module 300).
Blaser does not specify the use of the LED (light-emitting diode) chip as the element to be controlled beyond the general description of controlling hardware elements in paragraph 0056 and the use of an LED in paragraph 0074.
Liu teaches control of the LED (light-emitting diode) by the microprocessor (paragraph 0125 explains how the microprocessor 200 is used to control the light emitting diode D2).
It would have been obvious to one of ordinary skill before the effective filing date to use the LED as the element to be controlled as taught by Liu in the system of Blaser. The rationale to combine would be to allow different status of the LED lighting to be used to indicate different behavior (paragraph 0125 of Liu).
Regarding claim 2, Blaser teaches the method for data transmission by pulling a power line down to a ground line according to claim 1, wherein demodulating a waveform signal on a power supply VCC comprises the following sub-steps: acquiring a first level signal and a second level signal according to a level state of the power supply VCC, inverting the first level signal to obtain a first inverted level signal, and obtaining the demodulated signal according to the first inverted level signal and the second level signal (paragraph 0057 explains how the power is set to a high or low value to represent a “1” or a “0” to contain the data to be read as data bits from these values and paragraphs 0084-0085 explain how the reading is done by performing functions to the inverted signal to ensure that the data was sent without errors. The combination of these teachings renders these limitations to be obvious.).
Regarding claim 6, Blaser teaches the method for data transmission by pulling a power line down to a ground line according to claim 1, further comprising: determining a level state of the power supply VCC, when the power supply VCC is at a high level, controlling the power supply VCC to serve as an operation power supply to charge a digital power hold circuit; when the power supply VCC is at a low level, controlling the digital power hold circuit to serve as the operation power supply, with a requirement to ensure that time to pull the power supply VCC down to the level of the ground line is controlled to be shorter than time required for decreasing a voltage of the digital power hold circuit to a threshold level (paragraph 0057 explains the different levels of the power supply used to control the operations while paragraph 0059 explains specifically how the charging and the use of the power is switched based on the values of data being transmitted. Thus, the device can be charged or at rest as given in paragraph 0036. Paragraph 0070 explains the timing used to pull the power signal to ground within a specific amount of time.).
Allowable Subject Matter
Claims 3-5 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, taken alone or in combination, teaches the specifics claimed, especially “defining a power supply level as VPWR, and a system ground level as VGND, and acquiring a first turn-on voltage VT41, a second turn- on voltage VT42, a first trigger threshold V1 and a second trigger threshold V2; dividing the power supply VCC into two conditions: converting a voltage of the power supply VCC from VGND to VPWR, and the voltage of the power supply VCC from VPWR to VGND; when the voltage of the power supply VCC is converted from VGND to VPWR, acquiring the first level signal specifically comprises the following sub-steps: with the increase of VCC voltage, when VT41<VCC<V1, obtaining the first level signal at a high level, and inverting the first level signal to obtain the first inverted level signal at a low level; when V1<VCC, obtaining the first level signal at a low level, and inverting the first level signal to obtain the first inverted level at a high level; and acquiring the second level signal specifically comprises the following sub-steps: with the increase of the voltage of VCC, when VT42<VCC<V2,obtaining the second level signal at a high level, and when V2<VCC, obtaining the second level signal at a low level; when the voltage of the power supply VCC is converted from VPWR to VGND, acquiring the first level signal specifically comprises the following sub-steps: with the decrease of the voltage of VCC, when V1<VCC< VPWR, obtaining the first level signal at a low level, and inverting the first level signal to obtain the first inverted level signal at a high level; when VT41<VCC<V1, obtaining the first level signal at a high level, and inverting the first level signal to obtain the first inverted level at a low level; and acquiring the second level signal specifically comprises the following sub-steps: with the decrease of the voltage of VCC, when V2<VCC< VPWR, obtaining the second level signal at a low level, and when VT42<VCC<V2, obtaining the second level signal at a high level; when the first level signal is at a high level, the first inverted level signal is at a low level, and the demodulated signal is at a low level at the moment; when the first level signal is at a low level, the first inverted level signal is at a high level, and a level state of the demodulated signal is determined by the second level signal; and when the second level signal is at a high level, the level state of the demodulated signal is determined by the first inverted level signal; and when the second level signal is at a low level and the first inverted level signal is at a high level, the demodulated signal is at a high level at the moment” as recited in claim 3 and “a power signal demodulation circuit, configured to demodulate a waveform signal on a power supply VCC and output a demodulated signal, wherein the demodulated signal is sent to a data protocol decoding circuit; a bandgap reference circuit, configured to generate a reference voltage, wherein the reference voltage is sent to a voltage regulator circuit; a digital power hold circuit, configured to generate a power supply required by a digital circuit for operation, charge the digital power hold circuit when a power supply VCC is at a high level, and supply power to a digital circuit when the power supply VCC is at a low level; a chip ID storage circuit, configured to store an address of an LED chip of an LED driver circuit, and send the address to the data protocol decoding circuit for use; a voltage regulator circuit, configured to convert a voltage of a power supply into a regulated voltage for internal use, and supply the regulated voltage to other circuits except a digital power supply; an oscillator unit, configured to generate a clock signal to provide clock beats for the whole digital circuit operation; a data protocol decoding circuit, configured to decode the demodulated signal according to the clock signal and the address of the LED chip to acquire a control command of an LED control system; a logic control circuit, configured to generate corresponding display data according to a decoding command; and a digital data control circuit, configured to convert the display data into gray duty data for controlling brightness of an LED lamp, wherein the gray duty data is sent to the LED driver circuit for driving an LED” as recited in claim 7. All other claims are objected to as being dependent on an allowable base claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARUL H GUPTA whose telephone number is (571)272-5260. The examiner can normally be reached Monday through Friday, from 10 AM to 7 PM.
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/PARUL H GUPTA/Primary Examiner, Art Unit 2627
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