DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant’s claim for the benefit of prior-filed application 63/571,678 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
All claims are examined with an effective filing date of March 29, 2024.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sohi et al. (US 2014/0101390).
Regarding claim 1, Sohi teaches a computer-implemented method (the citations discussed below are executed in a computer architecture, see [0001], teaching that the method is implemented in a computer; see also “Referring now to FIGS. 1 and 4, the MLI circuit 24 may execute an MLI program 41 (for example, firmware or discrete logic) to further process each invalidation message generated by the standard cache coherence protocol. This program generally checks to see if a given invalidation message can be delayed and combined with other invalidation messages associated with the common region,” [0051]) for sidecar cache invalidations in a tenant context service architecture (MPEP 2111.02(II) provides that “If the body of a claim fully and intrinsically sets forth all of the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct definition of any of the claimed invention’s limitations, then the preamble is not considered a limitation and is of no significance to claim construction. Shoes by Firebug LLC v. Stride Rite Children’s Grp., LLC, 962 F.3d 1362, 2020 USPQ2d 10701 (Fed. Cir. 2020) (The court found that the preamble in one patent’s claim is limiting but is not in a related patent); Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See also Rowe v. Dror, 112 F.3d 473, 478, 42 USPQ2d 1550, 1553 (Fed. Cir. 1997) ("where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention, the preamble is not a claim limitation");” Therefore, for the purpose of interpreted claim 1, the phrase “for sidecar cache invalidations in a tenant context service architecture” lacks patentable weight; examiner notes that dependent claims do recite the limitations, and so the preamble would carry patentable weight for those claims, which will be addressed), the computer-implemented method comprising:
receiving a cache invalidation message (“Upon the generation of an invalidation message indicated by process block 42,” [0051]);
publishing the cache invalidation message to a cache invalidation repository based on a region identifier of a plurality of region identifiers associated with the cache invalidation repository ([0053] provides that the MLI circuit determines whether an invalidation message is associated with a particular region already in an MLI data structure, see Figs. 2 and 3, where [0056] provides if the current processor has permission to delay the invalidation, the invalidation message is combined with other invalidations from the same region, see Fig. 6 for example; the storage of the MLIR message in the MLI data structure reads on the publishing limitation);
receiving a cache invalidation polling request from a service associated with the region identifier (in the context of Fig. 8 showing an example invalidation, “At the given cache controllers 16 receiving of an MLIR message (for example, for processor P1), a combined acknowledgment message (AMLIR) analogous to the MLIR message is then returned as indicated by arrow 86 to the directory 20,” [0068]); and
providing, the cache invalidation message to the service associated with the region identifier (“Transmission of multi-line invalidation messages will occur when the data-race region is exited or if there is an exhaustion of memory resources for MLI data structure 26 (for example, if more invalidation messages have occurred for more regions than can be stored). In this case, the cache controller 16 issues a multi-line invalidation message (MLIR) 66, for example, in the form shown in FIG. 6, to the directory 20 indicated by arrow 78,” [0065] followed by “When this MLIR message is received by the directory 20, the directory 20 determines those other cache memories 14 sharing the cache lines to be invalidated and forwards the multi-line invalidation messages to the corresponding cache controllers 16 per arrow 80 causing them to invalidate the corresponding cache lines in their associated cache memories 14,” [0066]; for clarity of record, the claim limitation only requires that the cache invalidation message is supplied to the service associated with the region identifier; notably, there is no timing provided for when this invalidation message is supplied in relation to the polling request within the language of the claim).
Regarding claim 6, Sohi teaches the computer-implemented method of claim 1, and further teaches wherein each region identifier of the plurality of region identifiers is associated with at least one dedicated cache invalidation repository for the region identifier (Sohi Figs. 1 and 2 depict each processor containing a MLI circuit 24 containing MLI data structures for regions of memory).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, 7-9, 11, 13-17, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sohi in view of Guthrie et al. (US 2017/0177501).
Regarding claim 2, Sohi teaches the computer-implemented method of claim 1, but fails to teach wherein receiving the cache invalidation polling request from the service comprises receiving the cache invalidation polling request from a sidecar associated with the service.
Guthrie’s disclosure relates to providing a multiprocessor system that handles cache invalidation, and as such comprises analogous art in the same area of cache invalidation.
As part of this disclosure, Guthrie depicts a multiprocessor system in Fig. 2, where each processor core has an associated L2 cache, and Fig. 3 depicts the L2 cache and processor in further detail, where the L2 cache contains a sidecar logic, where “According to one embodiment of a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request,” [0009].
An obvious modification can be identified: incorporating sidecars to complement Sohi’s MLI circuit. Such a modification reads upon the limitation of the claim. Examiner also notes that due to this, the combination reads upon the preamble of claim 1, which now carries patentable weight due to claim 2’s recitation of a sidecar.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Guthrie’s sidecar logic for processing invalidation requests into Sohi’s MLI circuit, as the sidecar logic allows for processing for multiple individual hardware threads, not just a particular processor, see [0009], allowing finer granularity over invalidation request processing and handling potential race conditions.
Regarding claim 4, Sohi teaches the computer-implemented method of claim 1, further comprising receiving a registration request comprising the region identifier prior to receiving the cache invalidation polling request (Sohi Fig. 7 provides for a process for requesting delay permissions for a particular processor/region, including sending acknowledgment messages, see [0059,0060]).
Sohi fails to teach that this registration request is specifically a sidecar registration request.
Guthrie’s disclosure relates to providing a multiprocessor system that handles cache invalidation, and as such comprises analogous art in the same area of cache invalidation.
As part of this disclosure, Guthrie depicts a multiprocessor system in Fig. 2, where each processor core has an associated L2 cache, and Fig. 3 depicts the L2 cache and processor in further detail, where the L2 cache contains a sidecar logic, where “According to one embodiment of a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request,” [0009].
An obvious modification can be identified: incorporating sidecars to complement Sohi’s MLI circuit. Such a modification reads upon the limitation of the claim. Examiner also notes that due to this, the combination reads upon the preamble of claim 1, which now carries patentable weight due to claim 4’s recitation of a sidecar.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Guthrie’s sidecar logic for processing invalidation requests into Sohi’s MLI circuit, as the sidecar logic allows for processing for multiple individual hardware threads, not just a particular processor, see [0009], allowing finer granularity over invalidation request processing and handling potential race conditions.
Regarding claim 7, Sohi teaches the computer-implemented method of claim 1, but fails to teach wherein the service comprises a tenant context service sidecar.
Guthrie’s disclosure relates to providing a multiprocessor system that handles cache invalidation, and as such comprises analogous art in the same area of cache invalidation.
As part of this disclosure, Guthrie depicts a multiprocessor system in Fig. 2, where each processor core has an associated L2 cache, and Fig. 3 depicts the L2 cache and processor in further detail, where the L2 cache contains a sidecar logic, where “According to one embodiment of a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request,” [0009].
An obvious modification can be identified: incorporating sidecars to complement Sohi’s MLI circuit. Such a modification reads upon the limitation of the claim, as the sidecars are provided for each hardware thread, i.e. individual tenants in the processor. Examiner also notes that due to this, the combination reads upon the preamble of claim 1, which now carries patentable weight due to claim 7’s recitation of a tenant context service sidecar.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Guthrie’s sidecar logic for processing invalidation requests into Sohi’s MLI circuit, as the sidecar logic allows for processing for multiple individual hardware threads, not just a particular processor, see [0009], allowing finer granularity over invalidation request processing and handling potential race conditions.
Regarding claim 8, Sohi teaches the computer-implemented method of claim 1, but fails to teach wherein receiving the cache invalidation message comprises retrieving the cache invalidation message from a cache invalidation stream, wherein the cache invalidation message is stored in a memory for at least a predetermined period before publishing to the cache invalidation repository.
Guthrie’s disclosure relates to providing a multiprocessor system that handles cache invalidation, and as such comprises analogous art in the same area of cache invalidation.
As part of this disclosure, Guthrie depicts a multiprocessor system in Fig. 2, where each processor core has an associated L2 cache, and Fig. 3 depicts the L2 cache and processor in further detail, where the L2 cache contains a sidecar logic, where “According to one embodiment of a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request,” [0009].
An obvious modification can be identified: incorporating sidecars to complement Sohi’s MLI circuit and in particular allowing sidecars to pull requests from a shared queue. Such a modification reads upon the limitation of the claim, as the shared queue reads upon the memory storing the invalidation request, and the time before processing and buffering the invalidation requests into the sidecar reads upon period before publishing the invalidation request to the repository.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Guthrie’s sidecar logic for processing invalidation requests into Sohi’s MLI circuit, as the sidecar logic allows for processing for multiple individual hardware threads, not just a particular processor, see [0009], allowing finer granularity over invalidation request processing and handling potential race conditions.
Regarding claim 9, Sohi teaches an apparatus for sidecar cache invalidations in a tenant context service architecture (Fig. 1), the apparatus comprising at least one processor (Fig. 1,l processors 12) and the at least one processor causing the apparatus to at least perform the method of claim 2, incorporating the method of claim 1, and can therefore be rejected according to the same rationale, incorporating Guthrie.
Sohi fails to teach the apparatus comprising at least one memory including program code which cause the apparatus to perform the described method. The rationale of rejecting claim 2 utilizing Guthrie does not yet teach this feature.
As part of Guthrie’s disclosure, Guthrie discloses alternate embodiments to their disclosed invention including computer system executing program code stored on a computer-readable storage device including memory, see [0101,0102].
An obvious combination can be identified: combining Guthrie’s program code embodiment with Sohi’s disclosed invention. Such a combination reads upon the memory including program code.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Guthrie’s program code embodiment with Sohi’s cache invalidation disclosure. Both elements are available as prior art, and as Guthrie’s disclosure provides that one skilled in the art would recognize the program code embodiment as an obvious variant without departing from the scope of the implementation and capable of fulfilling its disclosure regarding the sidecar cache invalidation process, then the combination would lead to a predictable result: operating Sohi’s cache invalidation process, but embodied as program code, as disclosed by Guthrie to be within the skill of one skilled in the art.
Claim 11 and 13-15 are rejected according to the rationale of claim 4 and 6-8 respectively.
Regarding claim 16, the functional limitations of claim 16 are identical to the method of claim 1 and can therefore be rejected according to the same rationale. Sohi fails to teach where these functional limitations are embodied on at least one non-transitory computer-readable storage medium having computer coded instructions.
Guthrie’s disclosure relates to providing a multiprocessor system that handles cache invalidation, and as such comprises analogous art in the same area of cache invalidation.
As part of Guthrie’s disclosure, Guthrie discloses alternate embodiments to their disclosed invention including computer system executing program code stored on a computer-readable storage device including memory, see [0101,0102].
An obvious combination can be identified: combining Guthrie’s program code embodiment with Sohi’s disclosed invention. Such a combination reads upon the memory including program code.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Guthrie’s program code embodiment with Sohi’s cache invalidation disclosure. Both elements are available as prior art, and as Guthrie’s disclosure provides that one skilled in the art would recognize the program code embodiment as an obvious variant without departing from the scope of the implementation and capable of fulfilling its disclosure regarding the sidecar cache invalidation process, then the combination would lead to a predictable result: operating Sohi’s cache invalidation process, but embodied as program code, as disclosed by Guthrie to be within the skill of one skilled in the art.
Claim 17, 19, and 20 are rejected according to the same rationale of claims 2, 4, 6.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unaptenatalbe over Sohi in view of Guthrie and further in view of Jaskiewicz et al. (US 2019/0102297).
Regarding claim 5, the combination of Sohi and Guthrie teaches the computer-implemented method of claim 4, wherein the sidecar registration request further comprises a client identifier (Sohi Fig. 7 discloses a process for acquiring permissions for particular processors, where the directory records this permission, reading on a client identifier), but fails to teach wherein the client identifier comprises a role identifier and a role session name.
Jaskiewicz’s disclosure relates to a multi-node system with cache invalidation, and as such comprises analogous art.
As part of this disclosure, Jaskiewicz discloses in Fig. 1 a system for accessing a database, where multiple delivery nodes 50, each with their own name, can access the database, and a management node 10 provides content management, including invalidations, see also [0040,0041]. Of particular note, “A delivery node 50 may be implemented on the same host machine as management stage node and/or multiple delivery nodes may be implemented on the same host machine,” [0040].
An obvious modification can be identified: incorporating Jaskiewicz’s disclosure of different kind of nodes (management vs. delivery), and where the delivery nodes each have a name into Sohi’s disclosure. Such a modification reads upon the role (delivery vs. management) and name (as seen in Fig. 1) limitations of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Jaskiewicz’s different node roles/names into Sohi’s disclosure, as this allows for an additional way to identify/manage the individual processors.
Claim 12 is rejected according to the same rationale of claim 5
Allowable Subject Matter
Claims 3, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3, 10, and 18 recite, using claim 3 for example language, “broadcasting a cache key currently stored by the sidecar to at least a second sidecar associated with the service”.
While Guthrie’s disclosure relates to providing broadcasts of TLBIE requests by sidecar logics, no discussion of a key is found, and in a search of the art, no reference was found to address this feature.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kawaguchi (US 2010/0042771) discloses invalidating cache lines based on the region location in memory,
Wang et al. (US 2017/0242797) discloses identifying caches with a shared status of a cache line to invalidate instead of a general broadcast,
Truelove et al. (US 2021/0209031), Pape et al. (US 2022/0066947), Richardson et al. (US 2022/0214973), Blasco et al. (US 2023/0064603), Sandberg (US 2023/0409487), Horsnell et al. (CN 110770709), disclose invalidating cache entries based on different identifiers (address space, virtual machine, processes, etc.).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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