Response to Arguments
Applicant's arguments filed 03/18/2026 have been fully considered but they are not persuasive.
Applicant argued Kim fails to disclose “a first timing controller” and “a first power supply device configured to provide…..a first direct current (DC) voltage to the first timing controller based on the first AC power,”, which is incorrect. Applicant argued that “The Office Action maps the first timing controller of claim 1 to the first power module 310 of Kim, and the first power supply device of claim 1 to the rectifier circuit 311 of Kim. See Office Action at pgs. 2-3. However, the rectifier circuit 311 in Kim is integrated within the power module 310 itself. The rectifier circuit 311 receives AC power, rectifies it, and contributes to the power module's own output of DC power to the display 340. See Kim at [0046]-[0047]. Therefore fails to disclose each of the "first timing controller" and the "first power supply device" recited in claim 1.”, which is incorrect. Claim 1 does not specify or clarify specific feature or limit certain features only in “a first timing controller” which has a feature that a first power supply device configured to provide, based on a first alternating current (AC) power being transferred through a first AC power cable (FIG. 4, the first power module 310 (e.g., the first power module 310 of FIG. 3)) may include a rectifier circuit 311, rectifier circuit 311 may receive AC power from the external power source and may full-wave rectify the received AC power), a first direct current (DC) voltage to the first timing controller based on the first AC power (the processor 330 may determine whether the first power module 310 is abnormal, based on output power (hereinafter, referred to as a ‘first power’) of the first power module 310). As similar for second timing controller, a second timing controller; a second power supply device configured to provide, based on a second AC power being transferred though a second AC power cable, a second DC voltage to the second timing controller based on the second AC power (At time t1, the second power module 320 may enter the abnormal state due to a failure or the like. At time t1, the processor 330 may sense the abnormal state of the second power module 320, and the luminance of the display 340 may be reduced at a time t2, based on the control of the processor 330).
Furthermore, Applicant argued that Kim fails to disclose applying driving signals to the first timing controller and second timing controller as since in fig. 3, where in the signals are connected from the first timing controller 310 to processor 330 and second timing controller 320to processor 330. As since that the signals are connected between310, 320 and 330 in fig. 3, therefore, signals are applying to the first timing controller and the second timing controller.
To further assist the Applicant with the guidance with claim language interpretations so that the Applicant can add further/more details limitations from the specification to the claims to overcome the prior arts, the Examiner is presenting MPEP, section 2111, Claim Interpretation; Broadest Reasonable Interpretation as follow: “The court explained that “reading a claim in light of the specification, to thereby interpret limitations explicitly recited in the claim, is a quite different thing from reading limitations of the specification into a claim,' to thereby narrow the scope of the claim by implicitly adding disclosed limitations which have no express basis in the claim.” The court found that applicant was advocating the latter, i.e., the impermissible importation of subject matter from the specification into the claim.). See also In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997) (The court held that the PTO is not required, in the course of prosecution, to interpret claims in applications in the same manner as a court would interpret claims in an infringement suit. Rather, the “PTO applies to verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in applicant's specification.”)”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2021/0142704).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Kim et al. (US 2021/0142704), figs. 1-3, discloses a display device (FIG. 1, according to an embodiment, a large-screen display system 100) comprising: a first timing controller (FIG. 3, a display device 300 (e.g., the display device 110 of FIG. 1) may include a display 340 (e.g., a plurality of display modules (e.g., 111) of FIG. 1), and a processor 330); a first power supply device configured to provide, based on a first alternating current (AC) power being transferred through a first AC power cable (FIG. 4, the first power module 310 (e.g., the first power module 310 of FIG. 3)) may include a rectifier circuit 311, rectifier circuit 311 may receive AC power from the external power source and may full-wave rectify the received AC power), a first direct current (DC) voltage to the first timing controller based on the first AC power (the processor 330 may determine whether the first power module 310 is abnormal, based on output power (hereinafter, referred to as a ‘first power’) of the first power module 310); a second timing controller; a second power supply device configured to provide, based on a second AC power being transferred though a second AC power cable, a second DC voltage to the second timing controller based on the second AC power (At time t1, the second power module 320 may enter the abnormal state due to a failure or the like. At time t1, the processor 330 may sense the abnormal state of the second power module 320, and the luminance of the display 340 may be reduced at a time t2, based on the control of the processor 330); and a main board (fig. 1, power module) comprising at least one processor (330), wherein the at least one processor is configured to: based on the first AC power cable being detected as connected to the first AC power based on the first DC voltage transferred from the first timing controller ((FIG. 4, the first power module 310 (e.g., the first power module 310 of FIG. 3)), and based on the second AC power cable being detected as connected to the second AC power based on the second DC voltage transferred from the second timing controller, apply driving signals to the first timing controller and the second timing controller (At time t1, the second power module 320 may enter the abnormal state due to a failure or the like. At time t1, the processor 330 may sense the abnormal state of the second power module 320, and the luminance of the display 340 may be reduced at a time t2, based on the control of the processor 330).
Regarding claim 2, Kim et al. (US 2021/0142704), figs. 1-3, 12, discloses the display device of claim 1, wherein the at least one processor is further configured to, based on at least one of the first DC voltage not being transferred from the first timing controller or the second DC voltage not being transferred from the second timing controller, not apply the driving signals to the first timing controller and the second timing controller (The first display device 1210 may include a first processor 1211 (e.g., the processor 330 in FIG. 3), a first display 1213 (e.g., the display 340 in FIG. 3), and the first power module 1215 (e.g., the first power module 310 of FIG. 3) (since the second conversion circuit 315 may change the overload criterion of the first power module 310 by using the first sensing circuit 317, the second conversion circuit 315 may support normal transfer of the output of the first power module 310 at least until the processor 330 identifies the abnormal state of the second power module 320 and lowers the luminance of the display 340, while lowering the rating of the first power module 310).
Regarding claim 7, Kim et al. (US 2021/0142704), figs. 1-3, 12, discloses the display device of claim 1, further comprising: a first AC inlet board configured to receive the first AC power through the first AC power cable, and transfer the first AC power to the first power supply device; and a second AC inlet board configured to receive the second AC power through the second AC power cable, and transfer the second AC power to the second power supply device (At time t1, the second power module 320 may enter the abnormal state due to a failure or the like. At time t1, the processor 330 may sense the abnormal state of the second power module 320, and the luminance of the display 340 may be reduced at a time t2, based on the control of the processor 330) (the processor 330 may determine whether the first power module 310 is abnormal, based on output power (hereinafter, referred to as a ‘first power’) of the first power module 310. For example, the processor 330 may determine that the first power module 310 is in an abnormal state when a first signal generated from the first power is less than or equal to a first threshold value. In addition, the processor 330 may determine whether the second power module 320 is abnormal, based on output power (hereinafter, referred to as a ‘second power’) of the second power module 320).
Regarding claim 8, Kim et al. (US 2021/0142704), figs. 1-3, 12, discloses the display device of claim 7, wherein the main board, the first AC inlet board and the second AC inlet board are connected via daisy chain configuration (see Referring to FIG. 2, a first power module P121 and a second power module P122 of the display device 120 (e.g., 120 of FIG. 1) may share a load. For example, outputs of the first power module P121 and the second power module P122 are connected in parallel to each other to supply power to the display of the same display device. To this end, the rated power of the first power module P121 and the second power module P122 may be more than half of the rated power of the display device (e.g., 120)).
Allowable Subject Matter
Claims 3-6, 9-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest that the display device of claim 1, wherein the main board further comprises: an AND gate circuit comprising: a first input terminal configured to receive the first DC voltage from the first timing controller, a second input terminal configured to receive the second DC voltage from the second timing controller, and an output terminal, and wherein the at least on processor is further configured to detect whether the first AC power cable is connected to the first AC power and the second AC power cable is connected to the second AC power based on an output value of the AND gate circuit; the play device of claim 1, further comprising: a first cable connecting the first timing controller with the main board; and a second cable connecting the second timing controller with the main board, wherein the at least one processor is further configured to: apply video data and the driving signals to the first timing controller through the first cable and to the second timing controller through the second cable, respectively, and receive the first DC voltage from the first timing controller through the first cable and the second DC voltage from the second timing controller through the second cable; and/or the display device of claim 1, further comprising: a first cable connecting the first timing controller with the main board; a second cable connecting the second timing controller with the main board; a third timing controller; a third power supply device configured to apply, based on the first AC power being transferred through the first cable, a third DC voltage to the third timing controller based on the first AC power; a fourth timing controller; and a fourth power supply device configured to apply, based on the second AC power being transferred through the second cable, a fourth DC voltage to the fourth timing controller based on the second AC power, wherein the at least one processor is further configured to: based on the first AC power cable being detected as connected to the first AC power based on the first DC voltage transferred from the first timing controller and the third DC voltage transferred from the third timing controller, and based on the second AC power cable being detected as connected to the second AC power based on the second DC voltage transferred from the second timing controller and the fourth DC voltage transferred from the fourth timing controller, apply the driving signals to the first timing controller, the second timing controller, the third timing controller, and the fourth timing controller.
Claim 17 is allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN N CHOW/Primary Examiner, Art Unit 2627
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