CHIP FREQUENCY MODULATION METHOD AND APPARATUS OF COMPUTING DEVICE, HASH BOARD, COMPUTING DEVICE AND STORAGE MEDIUM

§102 §103

DETAILED ACTION Claims 1-20 are presented for examination. The present application is being examined under the AIA (America Invents Act) First Inventor to File. This Office Action is Non-Final. Claims 1 and 12 are independent claims. Claims 2-11, 13-20 are dependent claims. This action is responsive to the following communication: corresponding claims filed on 03-27-2025. Information Disclosure Statement The information disclosure statement (IDS) submitted on 03-27-2025 is in compliance with the provisions of 37 CFR 1.97 Continuation Application This application discloses and claims only subject matter disclosed in prior Application. Accordingly, this application constitutes a continuation claiming benefit which is acknowledged. However, Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) and/or 120 as follows: The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application which benefit is sought. The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551,32 USPQ2d 1077 (Fed. Cir. 1994) The disclosure of the prior-filed applications, Application Number(s) 17/250,071 and 17/973,047 fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this instant application. In particular, the priority applications cited above do not disclose a “frequency distribution state of frequencies” and “distribution map according to frequency distribution state” as currently claimed. Therefore, claims 9-10 and 19 of the instant application are not entitled to the benefit of the filing date of the priority applications cited above, which means claims 9-11 and 19-20 are only entitled to the benefit of the filing date of March 27, 2025. Claim Interpretation Claims 5-6, 8, 11, 16-18 and 20 recited the terms “whether” and “if”, where under the broadest reasonable interpretation (BRI) standard make the expression following the term as optional limitation under the plain and ordinary meaning of the term, thereby not narrowing the claim limitations following the term since they can be omitted. Indeed, dictionary defines the term “if” as a “conditional clause”. Similarly, the following terms also found to be deficient are: may, might, can, could, potentially, possible ….etc. In re Johnston, 77 USPQ2d 1788, 113 Ex parte Schulhauser, see MPEP 2111.04 (II) Therefore, provided applicant does intend to have this/these limitations to have patentable weight, the claims above must positively recite the claim limitation without invoking optional language. Once such term that courts have found to positively recite a condition is the term “when”. Such amendment may be made that complies with this requirement will not constitute a new grounds of rejection under 37 C.F.R. 1. Double Patenting The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b). Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). For faster processing of Terminal Disclaimer the USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/ patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/ eTD-info-I.jsp. PNG media_image1.png 18 19 media_image1.png Greyscale As per 1-9, 11-20 claims of the instant application, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-26 of U.S. Patent No. 11,502,693 (hereinafter, “Patent No. ‘693” ) and as per claims 1, 4-8,11-18 claims of the instant application, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,287,717 (hereinafter, “Patent No. ‘717”) . Although the claims at issue are not identical, they are not patentably distinct from each other because of the following: As per claim(s) 1, 12, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method of a computing device, the computing device comprising at least one chip, the chip comprising a plurality of cores, and the method comprising: operating each of the plurality of cores to execute computations at a current working frequency, wherein the current working frequency is one of a plurality of working frequencies; (Patent No. ‘693: Claim(s) setting a plurality of working frequencies of each of the plurality of cores of the operational chip of the computing device and causing each of the plurality of cores in the operational chip to work at a current working frequency to compute one or more Nonces; claim 1 ) & (Patent No. ‘717: the computing device comprising at least one chip configured with a plurality of frequencies, and the chip comprising a plurality of cores, the method comprising: operating each of the plurality of cores to run at a working frequency, the working frequency being one of the plurality of frequencies; claim(s) 1 ) receiving, from each of the plurality of cores, a result of a computation executed at the current working frequency; (Patent No. ‘693: a first result from the random numbers through an algorithm when the core submits one random number within the modulation period, the first result including a first feature; Claim(s) 2 ) & (Patent No. ‘717: determining a computing performance indicator of each of the plurality of cores at the working frequency based on a number of timeouts of each of the plurality of cores; claim(s) 1) for each of the plurality of cores, analyzing a computing performance indicator based on the result of the computation executed at the current working frequency; and (Patent No. ‘693: a first result from the random numbers through an algorithm when the core submits one random number within the modulation period, the first result including a first feature; Claim(s) 2) & (Patent No. ‘717: analyzing, for the calculation, whether a computing correct ratio of the calculation reaches a first correct ratio threshold or a second correct ratio threshold within a modulation period, the first correct ratio threshold being the same as or different from the second correct ratio threshold; ; claim(s) 3) for at least one of the plurality of cores, modulating the current working frequency of the at least one core up or down to a different working frequency of the plurality of working frequencies that is higher or lower than the current working frequency according to the computing performance indicator. (Patent No. ‘693: modulating the current working frequency of the at least one core up or down to a different working frequency of the plurality of working frequencies that is higher or lower than the current working frequency according to the computing performance indicator further comprises: when the computing correct ratio of the random numbers reaches the first correct ratio threshold, modulating the current working frequency of the core up to the upper working frequency; or when the computing correct ratio of the random numbers does not reach the second correct ratio threshold, modulating the current working frequency of the core down to the lower working frequency; Claim(s) 1 ) & (Patent No. ‘717: modulating, according to the computing performance indicator, at least one working frequency of at least one of the plurality of cores up or down to a different frequency of the plurality of frequencies; claim(s) 1) As per claim(s) 2, 13, Patent No. ‘693 discloses a chip frequency modulation method wherein the result of the computation comprises one or more random numbers generated by the core. (Patent No. ‘693: Claim(s) 7) As per claim(s) 3, 14, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method wherein the result of the computation comprises one or more Nonces generated by the core. (Patent No. ‘693: Claim(s) 1 ) & (Patent No. ‘717: claim(s) 2) As per claim(s) 4, 15, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method wherein the computing performance indicator comprises a computing correct ratio of the result of the computation. (Patent No. ‘693: Claim(s) 6) & (Patent No. ‘717: claim(s) 3) As per claim(s) 5, 16, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method wherein the analyzing the computing performance indicator based on the result of the computation executed at the current working frequency comprises: analyzing whether a computing correct ratio of the result of the computation reaches a first correct ratio threshold or a second correct ratio threshold within a modulation period, the first correct ratio threshold being the same as or different from the second correct ratio threshold, and wherein the modulating the current working frequency of the at least one core up or down comprises: modulating the working frequency of the at least one core up in response to that the computing correct ratio of the at least one core reaches the first correct ratio threshold; or modulating the working frequency of the at least one core down in response to that the computing correct ratio of the at least one core does not reach the second correct ratio threshold. (Patent No. ‘693: Claim(s) 6) & (Patent No. ‘717: claim(s) 3) As per claim(s) 6, 17 Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method the analyzing the computing performance indicator based on the result of the computation executed at the current working frequency comprises: determining whether the result of the computation is correct; adding a computing correct weight value to a reference node value when the result of the computation is correct at least once, and deducting a computing wrong weight value from the reference node value when the result of the computation is wrong at least once; and determining whether the reference node value of each of the plurality of cores reaches a computing correct threshold or a computing wrong threshold; wherein the modulating the current working frequency of the at least one core up or down comprises: modulating the working frequency of the at least one core up in response to that the reference node value reaches the computing correct threshold; or modulating the working frequency of the at least one core down in response to that the reference node value reaches the computing wrong threshold. (Patent No. ‘693: Claim(s) 10) & (Patent No. ‘717: claim(s) 5-6 ) As per claim(s) 7, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method further comprising: controlling an expected tolerant resident error ratio of each core by controlling a ratio of the computing correct weight value to the computing wrong weight value; controlling a modulation period by controlling an absolute value of the computing correct weight value and the computing wrong weight value; and controlling the modulation period by controlling an absolute value of the computing correct threshold and the computing wrong threshold, wherein the computing correct weight value is the same asor different from the computing wrong weight value, and the computing correct threshold is the same asor different from the computing wrong threshold. (Patent No. ‘693: Claim(s) 10) & (Patent No. ‘717: claim(s) 5-6 ) As per claim(s) 8, 18, Patent No. ‘693 and Patent No. ‘717 discloses a chip frequency modulation method further comprising: if at least one of the plurality of cores cannot run at a given working frequency, removing the given working frequency from the plurality of frequencies, or adjusting a level position of the given working frequency among the plurality of frequencies. (Patent No. ‘693: Claim(s) 5-6) & (Patent No. ‘717: claim(s) 8) As per claim(s) 9, 19, Patent No. ‘693 discloses a chip frequency modulation method further comprising: determining, after frequency modulation, a frequency distribution state of frequencies of the plurality of cores; and modulating a configuration of the frequencies of the plurality of cores according to the frequency distribution state of the plurality of cores and a frequency modulation mechanism, the frequency modulation mechanism being a correspondence relationship between the frequency distribution state of the plurality of cores and a corresponding frequency modulation. (Patent No. ‘693: Claim(s) 2-5) ) As per claim(s) 11, 20, Patent No. ‘693 discloses a chip frequency modulation method wherein the modulating the configuration of the frequencies of the plurality of cores comprises: determining whether a frequency distribution state is optimal by evaluating whether more than a predetermined ratio of the plurality of cores are configured with frequencies within a middle range of the plurality of working frequencies; in response to that the frequency distribution state is not optimal, either adding an optimized working frequency to the plurality of working frequencies, or modulating at least one core from a current working frequency to a different working frequency. (Patent No. ‘693: Claim(s) 5) Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 8, 12, 18 are rejected under 35 U.S.C. 102(a)(1)/(a)/(2) as being anticipated by U.S. Publication No. 2012/0079290 (hereinafter, “Kumar”). As per claim(s) 1,121, Kumar discloses a chip frequency modulation method of a computing device, the computing device comprising at least one chip, the chip comprising a plurality of cores, and the method comprising: operating each of the plurality of cores to execute computations at a current working frequency, wherein the current working frequency is one of a plurality of working frequencies; (abstract states “ a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores.” ) receiving, from each of the plurality of cores, a result of a computation executed at the current working frequency; (¶ [0026] states “monitor micro-architectural activities and determine if one or more core's V/F can be dynamically changed”, ¶s [0028] ) ) for each of the plurality of cores, analyzing a computing performance indicator based on the result of the computation executed at the current working frequency; and (¶s [0029]-[0030] discloses the process of performing an “analysis” based on at least information of threads scheduled to cores and whether “not to dynamically adjust any voltage/frequency combination” ) for at least one of the plurality of cores, modulating the current working frequency of the at least one core up or down to a different working frequency of the plurality of working frequencies that is higher or lower than the current working frequency according to the computing performance indicator. (¶ [0031] states “adjust at least one voltage/frequency pair for a given core, control instead passes to block 340. There, a new voltage and frequency pair may be calculated for the selected core(s).” As per claims 8, 18, Kumar discloses a chip frequency modulation method, further comprising: if at least one of the plurality of cores cannot run at a given working frequency, removing the given working frequency from the plurality of frequencies, or adjusting a level position of the given working frequency among the plurality of frequencies. (¶ [0031] states “adjust at least one voltage/frequency pair for a given core, control instead passes to block 340. There, a new voltage and frequency pair may be calculated for the selected core(s).” Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2012/0079290 (hereinafter, “Kumar”) in view of U.S. Publication No. 2016/0328209 (hereinafter, “Pape”). As per claim(s) 2, 13, Kumar does not distinctly disclose wherein the result of the computation comprises one or more random numbers generated by the core. However, Pape explicitly discloses a chip frequency modulation wherein the result of the computation comprises one or more random numbers generated by the core. (Fig. 1) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kumar and Pape because both references are in the same field of endeavor. Papes’s teaching of a computation that includes random numbers generators would enhance Kumar's system by allowing the system to implements simulations to improve or predict a variety of tasks. 2. Claim(s) 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2012/0079290 (hereinafter, “Kumar”) in view of U.S. Publication No. 2014/0281554 (hereinafter, “Maletsky”). As per claims 3, 14, Kumar does not distinctly disclose wherein the result of the computation comprises one or more Nonces. However, Maletsky explicitly discloses wherein the result of the computation comprises one or more Nonces. (¶ [0064]) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kumar and Pape because both references are in the same field of endeavor. Papes’s teaching of a computation that includes nonces would enhance Kumar's system by allowing the system to implement cryptographic operations, thus improving security. Claim(s) 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2012/0079290 (hereinafter, “Kumar”) in view of U.S. Patent No. 9,846,475 (hereinafter, “Kumar”). As per claims 4 and 15, Kumar does not distinctly disclose wherein the computing performance indicator comprises a computing correct ratio of the result of the computation. However, Kumar explicitly discloses wherein the computing performance indicator comprises a computing correct ratio of the result of the computation. (the modulation of the frequency may be proportional to the core stall ratio (e.g., stall vs. not stall); Col 3 lines 34-65) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kumar and Kumar because both references are in the same field of endeavor. Kumar’s teaching of frequency modulation based on a ratio would enhance Kumar's system by allowing the system to operate more efficiently. Claim(s) 9-11, 19 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2012/0079290 (hereinafter, “Kumar”) in view of U.S. Publication No. 2015/0198988 (hereinafter, “Dasnurkar”). As perc claim(s) 9, 19, Kumar discloses a chip frequency modulation method further comprising: determining, after frequency modulation, of frequencies of the plurality of cores; and modulating a configuration of the frequencies of the plurality of cores according to the of the plurality of cores and a frequency modulation mechanism, the frequency modulation mechanism being a correspondence relationship between of the plurality of cores and a corresponding frequency modulation. (ACPI tables may be extended such that each core may be controlled to operate at a different frequency and/or voltage for an asymmetric workload; ¶ [0012] ) Kumar does not distinctly disclose a frequency distribution state. However, Dasnurkar determining, after frequency modulation, a frequency distribution state of frequencies of the plurality of cores; and modulating a configuration of the frequencies of the plurality of cores according to the frequency distribution state of the plurality of cores and a frequency modulation mechanism, the frequency modulation mechanism being a correspondence relationship between the frequency distribution state of the plurality of cores and a corresponding frequency modulation. (FIG. 4 is a lookup table for core specific scaling for each operating frequency.) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kumar and Dasnurkar because both references are in the same field of endeavor. Dasnurkar’s teaching of look up table for applying specific frequency scaling would enhance Kumar's system by allowing the system to operate more efficiently. As per claim 10, Kumar as modified discloses a chip frequency modulation method wherein the modulating the configuration of the frequencies of the plurality of cores according to the frequency distribution state of the plurality of cores and the frequency modulation mechanism comprises: translating at least part of a distribution map of the frequency distribution state in a coordinate system of the distribution map according to the frequency distribution state of the plurality of cores after the frequency modulation and the frequency modulation mechanism. (Dasnurkar: FIG. 4 is a lookup table for core specific scaling for each operating frequency.) & (ACPI tables may be extended such that each core may be controlled to operate at a different frequency and/or voltage for an asymmetric workload; ¶ [0012] ) As per claim(s) 11, 20, Kumar as modified discloses a chip frequency modulation method wherein the modulating the configuration of the frequencies of the plurality of cores comprises: determining whether a frequency distribution state is optimal by evaluating whether more than a predetermined ratio of the plurality of cores are configured with frequencies within a middle range of the plurality of working frequencies; in response to that the frequency distribution state is not optimal, either adding an optimized working frequency to the plurality of working frequencies, or modulating at least one core from a current working frequency to a different working frequency. (Dasnurkar: FIG. 4 is a lookup table for core specific scaling for each operating frequency.) & (ACPI tables may be extended such that each core may be controlled to operate at a different frequency and/or voltage for an asymmetric workload; ¶ [0012] ) Allowable Subject Matter Over 35 USC § 102/103 Claims 5-7 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AUREL PRIFTI/Primary Examiner, Art Unit 2175 Aurel Prifti Primary Examiner Art Unit 2175 Tel. (571) 270-1743 Fax (571) 270-2743 aurel.prifti@uspto.gov 1 As per independent claim 12, this claim is substantially equivalent to method claim 1, because any additional feature(s) are present on any off the shelf general-purpose computer. Therefore, for at least this reason, claims 12 also stand rejected. Indeed, at least Fig. 1 illustrates a chip comprising a plurality of processing units.