DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2012/0188427 to Solhusvik (“Solhusvik”)), and further in view of U.S. Patent Application Publication No. 2021/0289157 to Ha (“Ha”).
Regarding claim 1, Solhusvik teaches an image sensor circuit, comprising a row driver and a pixel array, wherein the pixel array comprises a plurality of pixel units that are coupled to the driver and that have two conversion gain modes (the two modes are a low conversion gain mode and a high conversion gain mode, see paragraph [0021]); and further comprising:
a plurality of conversion gain selection circuits, wherein the pixel units in a same column of the pixel array are coupled to the conversion gain selection circuit through a column bus (paragraph [0011] teaches column gain selection circuitry and column circuitry, see Figures 1-2);
the driver is configured to drive the pixel unit to output a plurality of voltage signals in the two conversion gain modes (paragraph [0026], [0028] teach the drive a signal and the driving line); and
the conversion gain selection circuit is configured to output one analog signal and one digital signal based on the plurality of voltage signals, wherein the digital signal indicates a conversion gain mode of the pixel unit, and the analog signal represents an output voltage corresponding to the conversion gain mode (paragraph [0017] teaches outputting a logic “1” for high voltage signal and logic “0” for low voltage signal, the voltage level is analog in paragraph [0039] which represents the voltage level received by the comparator).
Allowable Subject Matter
Claims 2-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY R HSU whose telephone number is (571)270-3012. The examiner can normally be reached 9am-5pm.
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AMY R. HSU
Examiner
Art Unit 2664
/AMY R HSU/Primary Examiner, Art Unit 2638
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