DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
Allowable Subject Matter
Examiner finds the detailed claimed combination of recitations of the claims 10-20 clearly distinctions over the teachings of the prior art of record, therefore, allowable over the prior art of record. The examiner advises the applicant to amend the claim 1 to include the recitations of the claim 18 to make the claims 1-9 allowable over the prior art of record.
Claims 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Voogel et al. (US 10,963,411 B1).
The examiner relies on the entire teachings of the Voogel reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the Voogel reference to better understand the examiner’s position and the interpretations applied to the claimed invention.
The Voogel reference teaches functionally equivalent limitations/recitations of the claimed invention, when the examiner applies the Broadest Reasonable Interpretation, as follows:
CLAIMS 1-9
Voogel REF TEACHINGS
1.A multicore processor comprising:
Figs 1B/2 with accompanying description of “Programmable Device 100B”, see also figure 2
a set of artificial intelligence ("Al") accelerator cores;
Col 11, line 14, “DPE array 180 may include processing resources having …(AI) and/or machine learning (ML) capabilities …”
at least one Ethernet node;
Col 13, line 14, “PS 230 may also include peripherals for communication standards such as Ethernet…”
at least one central processing unit ("CPU"); and
Col 13, line 10, “PS 230 may provide dedicated data processing capabilities for the device 200”
a network on chip ("NoC") that networks the set of Al accelerator cores, the at least one Ethernet node, and the CPU,
Col 13, line 21, “PS 230 may be selectively connected to other subsystems of the device 200 by the …NoC interconnect system 120
wherein the CPU executes instructions to administrate Ethernet transfers over an Ethernet link for the set of Al accelerator cores using the at least one Ethernet node.
Col 13: line 14, “PS 230 may also include peripherals for communication standards such as Ethernet…” & line 21, “PS 230 may be selectively connected to other subsystems of the device 200 by the …NoC interconnect system 120”
2. The multicore processor of claim 1, wherein the Ethernet link comprises a first Ethernet link, and wherein the Ethernet transfers are performed without utilizing a host that is in communication with the multicore processor or a second Ethernet link connected to the host.
Obvious from the teachings of Col 12, line 64, “PCIe interface 222 may be used to exchange data between the PS 230 and one or more other devices or chips via the transceivers 150 according got to PCI protocol…”
3. The multicore processor of claim 1, wherein the NoC collects information from the Al accelerator cores for use by the CPU to administrate the Ethernet transfers.
Obvious from the teachings of Col 16, line 17, “provide programmable signal routing between the DPE array 182 and a number of other subsystems and circuits of the device 100B by the NoC interconnect system 120”, see also figure 4 & 1B with accompanying description
4. The multicore processor of claim 3, wherein the information collected from the Al accelerator cores comprises information from one or more of the Al accelerator cores, information from a physical grouping of Al accelerator cores, or information from a logical grouping of Al accelerator cores.
Obvious from the teachings of: Col 11, line 33, “DPE interconnects include circuitry (such as signal lines and switches) that can provide programmable signal routing within the DPE 182, and programmable signal routing with subsystems and circuits external to the DPE array 180”; Col 12, line 17, “SoC interface circuit 184 may provide programmable signal routing between the DPE array 182 and a number of other subsystem s and circuit of the device 100B by the Noc interconnect system 120” &Col 16, line 17, “provide programmable signal routing between the DPE array 182 and a number of other subsystems and circuits of the device 100B by the NoC interconnect system 120”; see also figure 4 & 1B with accompanying description
5. The multicore processor of claim 3, wherein the information collected from the Al accelerator cores comprises information accessed from memory of one or more of the Al accelerator cores or information from communications between Al accelerator cores.
Obvious from the teachings of: Col 11, line 33, “DPE interconnects include circuitry (such as signal lines and switches) that can provide programmable signal routing within the DPE 182, and programmable signal routing with subsystems and circuits external to the DPE array 180”; Col 12, line 17, “SoC interface circuit 184 may provide programmable signal routing between the DPE array 182 and a number of other subsystem s and circuit of the device 100B by the Noc interconnect system 120” &Col 16, line 17, “provide programmable signal routing between the DPE array 182 and a number of other subsystems and circuits of the device 100B by the NoC interconnect system 120”; see also figure 4 & 1B with accompanying description
6. The multicore processor of claim 3, wherein, based on the information collected from the Al accelerator cores, the CPU determines that one or more of the Al accelerator cores require access to data from an external system via the Ethernet link, and wherein the determination causes the CPU to execute the instructions.
Obvious from the teachings of: Col 11, line 33, “DPE interconnects include circuitry (such as signal lines and switches) that can provide programmable signal routing within the DPE 182, and programmable signal routing with subsystems and circuits external to the DPE array 180”; Col 12, line 17, “SoC interface circuit 184 may provide programmable signal routing between the DPE array 182 and a number of other subsystem s and circuit of the device 100B by the Noc interconnect system 120” &Col 16, line 17, “provide programmable signal routing between the DPE array 182 and a number of other subsystems and circuits of the device 100B by the NoC interconnect system 120”; see also figure 4 & 1B with accompanying description
7. The multicore processor of claim 3, wherein, based on the information collected from the Al accelerator cores, the CPU predicts that one or more of the Al accelerator cores will require access to data from an external system via the Ethernet link, and wherein the prediction causes the CPU to execute the instructions.
Obvious from the teachings of: Col 11, line 33, “DPE interconnects include circuitry (such as signal lines and switches) that can provide programmable signal routing within the DPE 182, and programmable signal routing with subsystems and circuits external to the DPE array 180”; Col 12, line 17, “SoC interface circuit 184 may provide programmable signal routing between the DPE array 182 and a number of other subsystem s and circuit of the device 100B by the Noc interconnect system 120” &Col 16, line 17, “provide programmable signal routing between the DPE array 182 and a number of other subsystems and circuits of the device 100B by the NoC interconnect system 120”; see also figure 4 & 1B with accompanying description
8. The multicore processor of claim 1, wherein the instructions to administrate Ethernet transfers comprise configuration instructions and transmit instructions, wherein the CPU executes the configuration instructions to configure the at least one Ethernet node to establish Ethernet communications over the Ethernet link with an external system, and
Obvious from the teachings of: Col 13, line 48, “reconfiguration circuitry 244…the PMC 240 may allow portions of the PL 210 to be reconfigured using a partial reconfiguration operation…the PL 210 can be loaded from the PS 230 via either a primary or secondary…such as PCIe or Ethernet”
wherein the CPU executes the transmit instructions to transmit messages to the external system over the Ethernet link after the Ethernet communications are established.
Obvious from the teachings of Col 13: line 14, “PS 230 may also include peripherals for communication standards such as Ethernet…” & line 21, “PS 230 may be selectively connected to other subsystems of the device 200 by the …NoC interconnect system 120”
9. The multicore processor of claim 8, wherein the configuration instructions cause the at least one Ethernet node to establish or close links, set procedures for MAC resolution, establish network protocols, select between transmission control protocol ("TCP") or user datagram protocol ("UDP") protocols, or set error handling procedures.
Obvious from the teachings of Col 15, line 45, “hard-wire circuits such as, for example, USB controller, Ethernet MACs, multi-rate (MR) Ethernet MACs, PCIe controllers, and CCIX controllers…may include…the Physical Layer, the Data Link Layer, and the Transaction Layer of the PCIe protocol…”
The examiner notes that the Voogel reference does not expressly or identically discloses/labels the claimed “multicore processor” (i.e., the Voogel reference teaches/discloses functionally equivalent “programmable device” may be formed on a signal die); however, as can be seen from the detailed teachings, the Voogel reference does disclose/teach the functionally/operationally equivalent recitations of the claimed “multicore processor” (i.e., what are the claimed/recited functions of the “multicore processor”?). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the Voogel reference (i.e., the Voogel reference at least teaches the programmable device that provides/performs the claimed functions of the claimed multicore processor) for the above detailed teachings and reasons discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
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