DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7, 11, 17, and 19 are objected to because of the following informalities:
CLAIM 7:
In line 4, replace “a” with --the--.
CLAIM 11:
In line 5, before “in” insert --biased--.
CLAIM 17:
In the penultimate and last line, replace “signal” with --voltage--.
CLAIM 19:
In lines 3, 6-7, and 9-10, replace “provided by the current source” with --flowing through the bias transistor--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 11-13, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshizawa (JP 4848692B2 with included translation).
In re Claim 1, Yoshizawa teaches a charge pump as seen in Figure 1, comprising: a first capacitor (C1), having a first terminal and a second terminal; a current controlling transistor (M1), having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor (as seen in Figure 1), and the second terminal is coupled to a ground reference (as seen in Figure 1); an overcurrent protection circuit, comprising a current source (CM1) and a bias transistor (M2), wherein: the current source has a first terminal, a second terminal and a control terminal (gates of M3-M5), wherein the first terminal is coupled to a power supply (as seen in Figure 1); the bias transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the current source (as seen in Figure 1), the second terminal is coupled to the ground reference (as seen in Figure 1), and the control terminal is coupled to both the first terminal of the bias transistor and the control terminal of the current controlling transistor (as seen in Figure 1).
In re Claim 2, Yoshizawa teaches a first transistor SW3, a second transistor SW1 (its first terminal connected to ground via M3 and M2), and fourth transistor SW4 as claimed (the highlighted portion on Page 2 of the translation teaches the switches SW1, SW3, and SW4 are each transistors with control terminals).
In re Claim 3, Yoshizawa teaches the first transistor SW3 and the second transistor SW1 are turned on and off simultaneously, and the current controlling transistor M1 and the fourth transistor SW4 are turned on and off simultaneously as seen in Figure 6.
In re Claim 4, Yoshizawa teaches a second capacitor C2 as claimed.
In re Claim 5, the value of “a first reference voltage” is not defined and is considered arbitrary. Therefore the voltage at the first input of C1 is considered larger than said arbitrary undefined value.
In re Claim 6, Yoshizawa teaches a control circuit ( 3 and 10) having an input terminal and an output terminal, wherein the input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), and the output terminal is coupled to the control terminal (gate connection of M3-M5) of the current source CM1 to provide a current controlling signal based on a voltage at the first terminal of the first capacitor (highlighted portion of pages 6-7 of translation).
In re Claim 7, Yoshizawa teaches the control circuit comprises: a first comparator (3), having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), the second input terminal is configured to receive a first reference voltage (7), and an output terminal is configured to provide a first comparison signal; and a second comparator (10), having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), the second input terminal is configured to receive a second reference voltage (voltage at C4 and R3), and an output terminal is configured to provide a second comparison signal; wherein the current controlling signal comprises the first comparison signal and the second comparison signal (highlighted portion of pages 6-7 of translation).
In re Claim 11, Yoshizawa teaches an overcurrent protection circuit used with a charge pump, wherein the charge pump comprises a first capacitor (C1) and a current controlling transistor (M1) coupled between a first terminal of the capacitor and a ground reference, the overcurrent protection circuit comprising: a current source (CM1) , having a first terminal, a second terminal and a control terminal (gates of M3-M5), wherein the first terminal is coupled to a power supply (as seen in Figure 1), and the control terminal is biased in response to a voltage at the terminal of the capacitor (highlighted portion of pages 6-7 of translation); a bias transistor (M2) having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the current source, the second terminal is coupled to the ground reference, and the control terminal is coupled to both the first terminal of the bias transistor and a control terminal of the current controlling transistor (as seen in Figure 1).
In re Claim 12, Yoshizawa teaches a control circuit ( 3 and 10) having an input terminal and an output terminal, wherein the input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), and the output terminal is coupled to the control terminal (gate connection of M3-M5) of the current source CM1 to provide a current controlling signal based on a voltage at the first terminal of the first capacitor (highlighted portion of pages 6-7 of translation).
In re Claim 13, Yoshizawa teaches the control circuit comprises: a first comparator (3), having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), the second input terminal is configured to receive a first reference voltage (7), and an output terminal is configured to provide a first comparison signal; and a second comparator (10), having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the first capacitor (via R1, SW4 when turned on, and via current path through C1 from second terminal to first terminal), the second input terminal is configured to receive a second reference voltage (voltage at C4 and R3), and an output terminal is configured to provide a second comparison signal; wherein the current controlling signal comprises the first comparison signal and the second comparison signal (highlighted portion of pages 6-7 of translation).
In re Claim 17, Yoshizawa teaches a control method of an overcurrent protection circuit used with a charge pump, comprising: generating a current controlling signal based on a voltage at a terminal of a capacitor of the charge pump (via output from 3 and 10, highlighted portion of pages 6-7 of translation); generating a current flowing through a bias transistor (M2) based on the current controlling signal (highlighted portion of pages 6-7 of translation); mirroring the current flowing through the bias transistor to a current controlling transistor (M1) coupled between the terminal of the capacitor and a ground reference (highlighted portion of pages 6-7 of translation).
Allowable Subject Matter
Claims 8-10, 14-16, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In re Claims 8, 9, 14, and 15, Yoshizawa fails to teach when the voltage at the first terminal of the first capacitor is larger than both the first reference voltage and the second reference voltage, the current source provides a first current; when the voltage at the first terminal of the first capacitor is smaller than the first reference voltage but is larger than the second reference voltage, the current source provides a second current; and when the voltage at the first terminal of the first capacitor is smaller than both the first reference voltage and the second reference voltage, the current source provides a third current; wherein the first current is smaller than the second current, the second current is smaller than the third current, and the first reference voltage is larger than the second reference voltage.
In re Claims 10 and 16, Yoshizawa teaches a first power transistor M4, a second power transistor M3, a third power transistor M5, a fifth power transistor M6, and a sixth power transistor M7. Yoshizawa does not additionally teach a fourth power transistor arranged as claimed with the other power transistors.
In re Claims 18-20, Yoshizawa fails to teach that the first comparator 3 specifically compares the voltage at the first terminal of C1 with the first reference voltage 7, that the second comparator 10 specifically compares the voltage at the first terminal of C1 with the first reference voltage (voltage at C4 and R3), and that the first reference voltage is larger than the second reference voltage.
Conclusion
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/CHRISTOPHER J CLARK/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
