DETAILED ACTION
This communication is responsive to the application # 19/093,416 filed on March 28, 2025. Claims 1-20 are pending and are directed toward SYSTEM AND METHOD FOR ENCODING AND DECODING IN COMMUNICATION PROTOCOL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Marshall et al. (4,868,784, Sep. 19, 1989) from IDS, hereinafter referred to as Marshall.
As per claim 1, Marshall teaches a system for encoding and decoding in a communication protocol (Encoding and decoding hardware is provided which allows the data to be selectively companded according to the micro-255 law or to the A law, both prior to transmission and after receipt. Marshall, ABSTRACT), the system comprising:
a transmitter comprising (it should be apparent that serial data may be transmitted from more than two serial output terminals, all of said terminals being associated with only a single port address. Marshall, Column 24, lines 29-36):
a transmit data buffer to store a data (Once stages FIFO0 and FIFOl are loaded with the desired data, a framing pulse (either external or internal) will generate transmit register load signal SXLD, as discussed above relative to FIG. 4, for serial output via buffers 156 to serial output terminals DX0 and DXl respectively, Marshall, Column 20, lines 57-63);
an encoding circuitry operatively coupled to the transmit data buffer (On the transmit side, external data bus D, via lines Ds,is connected to an input of multiplexer 106, and is connected to encoder 108. Encoder 108, as will be explained in greater detail below, is a digital encoder used in performing the companding function used in certain communications applications, Marshall, Column 13, lines 28-33), wherein the encoding circuitry is to:
receive the data from the transmit data buffer (Encoder 108 performs the opposite function of decoder 116, relative to the companding of data according to the u-255 law and the A law, as discussed above relative to decoder 116. The output of encoder 108, eight bits wide, is connected to the other input of multiplexer 106. Similarly as decoder 116, bit CR(14) of control register 118 controls whether encoder
108 performs its function according to the u-255 law or the A-law. Marshall, Column 20, lines 29-37); and encode the data based on a selected encoding method (Bit CR(12) of control register 118 determines whether the output of multiplexer 106 corresponds to the output of encoder 108, or to the nonencoded data from lines D, of external data bus D. Marshall, Column 20, 37-40); and
a transmit shift register operatively coupled to the encoding circuitry, wherein the transmit shift register is to receive the encoded data and transmit the encoded data in the bitwise manner (The shifter S receives a 16-bit input Si from D-Bus and produces a 32-bit output So which is the input Si shifted from zero to fifteen places to the left. Left-shifted data is zero-filled, i.e., all right-hand bit positions are filled with zeros when data is shifted out to the left. A unique feature is that the high-order bit is sign extended during shift operations. The ALU operates in twos-complement. The shifter S includes a shift control Sc loaded with a four-bit value from P-Bus via lines Sp so an arithmetic instruction can directly define the number of bits shifted in the path from D-Bus to the ALU-b input. Marshall, Column 20, 24-35); and
a receiver comprising:
a receive shift register to receive the encoded data (On the receive side of the serial port, a pair of shift registers each receive serial data at the serial input terminals; at the end of the data frame, the contents of the shift registers are loaded into intermediate receive registers. Marshall, ABSTRACT);
a decoding circuitry operatively coupled to the receive shift register (Serial input terminals ORO and DRl are connected to receive shift registers RS0 and RSI, respectively. Receive shift registers RS0 and RSI are each eight-bit serial-in parallel-out shift registers, as are well known in the art. Marshall, Column 13, 12-16), wherein the decoding circuitry is to:
receive the encoded data from the receive shift register in a parallel manner; and decode the encoded data based on a selected decoding method (The output of multiplexer 104 is connected to an input of multiplexer 114, and to the input of decoder 116. Decoder 116, as will be discussed in greater detail below, is a digital decoder used in decoding data which has been encoded by the companding function used in certain communications applications, into a form useful by the remainder of microcomputer 10. Multiplexer 104 allows data from either of the receive registers RR0 or RRl, or data from stage FIFOO, to be communicated to external data bus D, with such data to be either decoded or not decoded. Marshall, Column 13, 34-64); and
a receive data buffer operatively coupled to the decoding circuitry, wherein the receive data buffer is to receive the decoded data (Control register 118 is also connected to external data bus D via lines D, and are connected to an input of multiplexer 114 for communication of its contents to microcomputer 10. Marshall, Column 13, 65-68).
As per claim 2, Marshall teaches the system of claim 1, wherein the encoding circuitry comprises a first control register to provide a first control signal; and wherein the selected encoding method is selected based on the first control signal from the first control register (Marshall, Column 20, 37-40).
As per claim 3, Marshall teaches the system of claim 2, wherein the transmitter comprises a multiplexer to selectively output the data or the encoded data to the transmit shift register based on the first control signal (Marshall, Column 20, 37-40).
As per claim 4, Marshall teaches the system of claim 2, wherein the encoding circuitry comprises: a first reference register to store a first encoding data; and a second reference register to store a second encoding data; wherein the encoding circuitry is to encode the data based on at least one of the first encoding data and the second encoding data (Marshall, Column 20, 34-37).
As per claim 5, Marshall teaches the system of claim 4, wherein the decoding circuitry comprises a second control register to provide a second control signal; and wherein the selected decoding method is selected based on the second control signal from the second control register (Marshall, Column 18, 56-65).
As per claim 6, Marshall teaches the system of claim 5, wherein the receiver comprises a multiplexer to selectively output the encoded data or the decoded data to the receive data buffer based on the first control signal (Marshall, Column 18, 56-65).
As per claim 7, Marshall teaches the system of claim 5, wherein the decoding circuitry comprises: a first reference register to store a first decoding data; a second reference register to store a second decoding data; and a third reference register to store a third decoding data; wherein the decoding circuitry is to decode the encoded data based on at least one of the first decoding data, the second decoding data, and the third decoding data (Marshall, Column 18, 40-55).
As per claim 8, Marshall teaches the system of claim 1, comprising a baud rate generator for generating a baud rate for the system, wherein the transmit shift register is to transmit the encoded data in the bitwise manner based on the baud rate (Marshall, Column 5, 10-20).
As per claim 9, Marshall teaches the system of claim 8, wherein the receive shift register is to transmit encoded data to the decoding circuitry in the bitwise manner based on the baud rate (Marshall, Column 5, 1-9).
As per claim 10, Marshall teaches the system of claim 8, wherein the baud rate generator generates the baud rate based on an external clock signal (Alternatively, an externally generated clock signal of up to 20 MHz may be applied to the X2 input to control such timing, in lieu of a crystal connected between Xl and X2. Marshall, Column 4, 58-61).
Claims 11-20 have limitations similar to those treated in the above rejection, and are met by the references as discussed above, and are rejected for the same reasons of anticipation as used above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OLEG KORSAK whose telephone number is (571)270-1938. The examiner can normally be reached on Monday-Friday 7:30am - 5:00pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rupal Dharia can be reached on (571) 272-3880. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OLEG KORSAK/
Primary Examiner, Art Unit 2492
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