DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 11 of U.S. Patent No. 12292638. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by or obvious in view of the claims of the copending application as follows.
Regarding claim 1, Claims 1, 2, and 11 of the patent recite an array substrate, comprising: a base substrate, comprising a display area and a peripheral area located at a periphery of the display area; a driving circuit layer, located at one side of the base substrate, and located in the display area, wherein the driving circuit layer comprises a plurality of data lines and a plurality of scanning lines, the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data lines and the scanning lines intersect with each other to define a plurality of sub-pixel areas; a metal layer, located at one side of the driving circuit layer away from the base substrate, and located in the display area, wherein the metal layer comprises a plurality of metal blocks arranged at intervals (lines 1-18 in claim 1 of the patent) and a plurality of touch control signal lines (lines 27-28 of claim 1 of the patent), and the metal blocks are located at intersections of the data lines and the scanning lines; (lines 18-20 in claim 1 of the patent) a signal lead, located at the side of the base substrate, and located in the peripheral area, wherein the signal lead comprises a data lead and a scanning lead, the data lead is connected to the data lines and is arranged in a same layer as the data lines, and the scanning lead is arranged in a same layer as the scanning lines; and a touch control lead, located at the side of the base substrate, and located in the peripheral area, wherein the touch control lead is connected to the touch control signal lines and is arranged in a same layer as the touch control signal lines; wherein orthographic projections, on the base substrate, of the data lead, the scanning lead and the touch control lead at least partially overlap with each other (lines 3-16 in claim 11 of the patent).
Regarding claim 2, Claims 1, 2, and 11 of the patent recite wherein orthographic projections of the touch control signal lines on the base substrate are located outside of orthographic projections of the sub-pixel areas on the base substrate, and the orthographic projections of the touch control signal lines on the base substrate at least partially overlap with orthographic projections of the data lines on the base substrate (lines 1-7 in claim 2 of the patent); and any one of the metal blocks comprises a touch control connecting metal piece and a metal spacer piece, the touch control connecting metal piece is connected to a touch control signal line in the touch control signal lines, and the metal spacer piece is spaced apart from the touch control signal lines (lines 28-33 in claim 1 of the patent).
Claims 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 11 of U.S. Patent No. 12292638 in view of Lee et al. (US Pub. 20080158199, Lee).
Regarding claim 12, Claims 1, 2, and 11 of the patent recite an array substrate, comprising: a base substrate, comprising a display area and a peripheral area located at a periphery of the display area; a driving circuit layer, located at one side of the base substrate, and located in the display area, wherein the driving circuit layer comprises a plurality of data lines and a plurality of scanning lines, the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data lines and the scanning lines intersect with each other to define a plurality of sub-pixel areas; a metal layer, located at one side of the driving circuit layer away from the base substrate, and located in the display area, wherein the metal layer comprises a plurality of metal blocks arranged at intervals (lines 1-18 in claim 1 of the patent) and a plurality of touch control signal lines (lines 27-28 of claim 1 of the patent), and the metal blocks are located at intersections of the data lines and the scanning lines; (lines 18-20 in claim 1 of the patent) a signal lead, located at the side of the base substrate, and located in the peripheral area, wherein the signal lead comprises a data lead and a scanning lead, the data lead is connected to the data lines and is arranged in a same layer as the data lines, and the scanning lead is arranged in a same layer as the scanning lines; and a touch control lead, located at the side of the base substrate, and located in the peripheral area, wherein the touch control lead is connected to the touch control signal lines and is arranged in a same layer as the touch control signal lines; wherein orthographic projections, on the base substrate, of the data lead, the scanning lead and the touch control lead at least partially overlap with each other (lines 3-16 in claim 11 of the patent).
Claims 1, 2, and 11 of the patent do not explicitly teach that the driving circuit layer further comprises: a gate layer, located at the side of the base substrate, wherein the scanning lines are arranged in a same layer as the gate layer, the gate layer comprises a gate, and the scanning lines are connected to the gate; a gate insulating layer, located at one side of the gate layer away from the base substrate, wherein the gate insulating layer covers a surface of the gate layer; an active layer, located at one side of the gate insulating layer away from the base substrate; and a source-drain layer, comprising a source covering one end of the active layer, and a drain covering another end of the active layer, wherein the data lines are arranged in a same layer as the source-drain layer, and the data lines are connected to the drain.
However, Lee teaches (in figure 2-3) forming a driving circuit layer to include a gate layer (gate wiring 320, 321, and 323), located at the side of the base substrate, wherein the scanning line (gate lines 320) is arranged in a same layer as the gate layer, the gate layer comprises a gate (gate electrode 321), and the scanning line is connected to the gate; a gate insulating layer (gate insulating layer 330), located at one side of the gate layer away from a base substrate (first insulating substrate 310), wherein the gate insulating layer covers a surface of the gate layer; an active layer (semiconductor layer 341), located at one side of the gate insulating layer away from the base substrate; and a source-drain layer (Data wiring 350, 351, 352, 353 and 354), comprising a source (source electrode 351) covering one end of the active layer, and a drain (A drain electrode 352) covering another end of the active layer, wherein a data line (data line 350) is arranged in a same layer as the source-drain layer, and the data line is connected to the drain.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include gate, gate electrode, gate insulating film, data line, source, and drain of Kimn the device of claims 1, 2, and 11.
The motivation would have been to provide a means of driving pixels in the display panel.
Claims 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 11 of U.S. Patent No. 12292638 in view of Kuroe et al. (US Pub. 20210341804, Kuroe).
Regarding claim 19, Claims 1, 2, and 11 of the patent recite an array substrate, comprising: a base substrate, comprising a display area and a peripheral area located at a periphery of the display area; a driving circuit layer, located at one side of the base substrate, and located in the display area, wherein the driving circuit layer comprises a plurality of data lines and a plurality of scanning lines, the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data lines and the scanning lines intersect with each other to define a plurality of sub-pixel areas; a metal layer, located at one side of the driving circuit layer away from the base substrate, and located in the display area, wherein the metal layer comprises a plurality of metal blocks arranged at intervals (lines 1-18 in claim 1 of the patent) and a plurality of touch control signal lines (lines 27-28 of claim 1 of the patent), and the metal blocks are located at intersections of the data lines and the scanning lines; (lines 18-20 in claim 1 of the patent) a signal lead, located at the side of the base substrate, and located in the peripheral area, wherein the signal lead comprises a data lead and a scanning lead, the data lead is connected to the data lines and is arranged in a same layer as the data lines, and the scanning lead is arranged in a same layer as the scanning lines; and a touch control lead, located at the side of the base substrate, and located in the peripheral area, wherein the touch control lead is connected to the touch control signal lines and is arranged in a same layer as the touch control signal lines; wherein orthographic projections, on the base substrate, of the data lead, the scanning lead and the touch control lead at least partially overlap with each other (lines 3-16 in claim 11 of the patent).
Claims 1, 2, and 11 of the patent do not explicitly teach that the array substrate is provided in a display panel of a display device.
However, Kuroe teaches (in figure 3) providing an array substrate (array substrate 21 and the elements formed thereon) in a display panel (liquid crystal panel 11) of a display device (liquid crystal display 10).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the array substrate of claims 1, 2, and 11 of the patent in a display panel of a display device.
The motivation would have been to provide an image to a user.
Allowable Subject Matter
Claim 15 is allowed.
Claims 3-10, 13, 14 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 15 and claims 3-10, 13, 14 and 16-18, Kuroe et al. (US Pub. 20210341804, Kuroe) teaches (in figures 1-2 and 11-15) an array substrate, comprising: a base substrate (421), comprising a display area (AA) and a peripheral area (NAA) located at a periphery of the display area; a driving circuit layer (26 and 27/427), located at one side of the base substrate, and located in the display area, wherein the driving circuit layer comprises a plurality of data lines (27/427) and a plurality of scanning lines (26), the plurality of data lines extend along a first direction (Y direction) and are arranged at intervals along a second direction (X direction), the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data line and the scanning line intersect with each other to define a plurality of sub-pixel areas (PX); and a metal layer (39 and 40), located at one side of the driving circuit layer away from the base substrate, and located in the display area, wherein the metal layer comprises a plurality of metal blocks (portions of 39 and 40 overlapping spacers 33) arranged at intervals.
Miyamoto (US Pub. 20170153482) teaches (in figure 2) forming spacers (SP) at the intersection of data lines (SL) and scanning lines (G1) in order to avoid reduction of an area of aperture (paragraph 85).
Hsu et al. (US Pub. 20190386032) teaches (in figures 4A-4B) a signal lead (F11, F21, and F31), located at a side of the base substrate, and located in a peripheral area, wherein the signal lead comprises a data lead (F21), the data lead is connected to data lines (DL) and is arranged in a same layer as the data lines; and a touch control lead (F11), located at the side of the base substrate, and located in the peripheral area, wherein the touch control lead is connected to the touch control signal lines (TP) and is arranged in a same layer as the touch control signal lines; wherein orthographic projections, on the base substrate, of the data lead, and the touch control lead at least partially overlap with each other.
Yang et al. (CN105652544A) (in figures 1 and 2) a signal lead (leads shown in the non-display area in figure 1 and figure 2 which is the cross section taken at line AA), located at the side of a base substrate, and located in the peripheral area, wherein the signal lead comprises a data lead (“Data”) and a scanning lead (“Gate”), the data lead is connected to the data lines, and a touch control lead (“TPM”), located at the side of the base substrate, and located in the peripheral area, wherein the touch control lead is connected to the touch control signal lines; wherein orthographic projections, on the base substrate, of the data lead, the scanning lead and the touch control lead at least partially overlap with each other (see figure 2).
However, Yang teaches against such an arrangement since arranging the data, scanning, and touch control lead to overlap reduces UV transmittance, increase the risk of product defects, and raises the requirements for the precision of exposure equipment.
As such the prior art taken alone or in combination fails to teach or fairly suggest to one of ordinary skill in the art at the time of filing a display in which wherein orthographic projections, on the base substrate, of the data lead, the scanning lead and the touch control lead at least partially overlap with each other in combination with the other required elements of the claims.
Conclusion
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/ALEXANDER P GROSS/Primary Examiner, Art Unit 2871
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