The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar (US Patent Application 20240160431).
As per claim 1, Kumar teaches a method [method shown, fig. 3] comprising:
loading, by a central processing unit (CPU) of a first chiplet of a superchip, a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip [0016, 0020, fig. 2-3, as pointed out and shown in figures 2 and 3, the firmware controller can load the boot firmware image 222 from memory 212 as well as boot firmware image 222 in memory 210. For example, boot controller 203 can load boot firmware image 222 from memory 212 of management controller 210. In some examples, boot controller 203 can be coupled to memory 212 using interface 230. As well as, controller 210 can execute management controller image 224 from memory 220 at boot].
initializing, by the CPU, the first chiplet based on the first boot code [0028, 0039, fig. 3, as pointed out the management controller can be initialized from the boot firmware. For example, firmware executing on management controller 210 can initialize management controller 210 by allocating Address Range A to store a boot image copied from a region in storage 220].
initializing, by the CPU, the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip [0026, 0027, fig. 3, from the interface specific configuration can be received where it can then be applied to initialize the memory 220 with management controller 220 with boot image 222. For example, management controller 210 can apply a configuration whereby accesses via interface 230 from boot processor 203 can be sent to Address Range A allocated for boot firmware image 222].
As per claim 8, Kumar teaches a superchip [200, fig. 2] comprising:
a compute chip [202, fig. 2].
a first chiplet [210, fig. 2].
and a second chiplet [220, fig. 2].
wherein the first chiplet comprises a central processing unit (CPU) [204, fig. 2] configured to:
load a first boot code of the first chiplet and a second boot code of the second chiplet [0016, 0020, fig. 2-3, as pointed out and shown in figures 2 and 3, the firmware controller can load the boot firmware image 222 from memory 212 as well as boot firmware image 222 in memory 210. For example, boot controller 203 can load boot firmware image 222 from memory 212 of management controller 210. In some examples, boot controller 203 can be coupled to memory 212 using interface 230. As well as, controller 210 can execute management controller image 224 from memory 220 at boot].
initialize the first chiplet based on the first boot code [0028, 0039, fig. 3, as pointed out the management controller can be initialized from the boot firmware. For example, firmware executing on management controller 210 can initialize management controller 210 by allocating Address Range A to store a boot image copied from a region in storage 220].
and initialize the second chiplet based on the second boot code via first configuration instructions sent through the compute die of the superchip [0026, 0027, fig. 3, from the interface specific configuration can be received where it can then be applied to initialize the memory 220 with management controller 220 with boot image 222. For example, management controller 210 can apply a configuration whereby accesses via interface 230 from boot processor 203 can be sent to Address Range A allocated for boot firmware image 222].
As per claim 15 they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claim 15 is also anticipated by Kumar for the same reasons set forth in the rejected claims above.
To help with prosecution of the application, additional rejection is given below
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7-8, 14-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iyengar (US Patent Application 20190095220).
As per claim 1, Iyengar teaches a method [500, fig. 5] comprising:
loading, by a central processing unit (CPU) of a first chiplet of a superchip, a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip [0033, as pointed out and shown in figure 1, the SOC 100 includes CPUSS 105 with boot loader BL1a in memory 150 as well as BL0 in memory 160].
initializing, by the CPU, the first chiplet based on the first boot code [0033, 0035 as pointed out, the first bootloader BL1a can be initialized. For example, CPU core 111 (e.g., as initialized by BL0) executes BL1a].
initializing, by the CPU, the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip [0035, 0075-0077, fig. 5 as pointed out the first processor executed some boot code where the second processor is connected to the first processor and receive service call or information to execute the next boot code. For example, in FIG. 1A, CPU core 111 (e.g., as initialized by BL0) executes BL1a. CPU core 111 further executes BL2, BL3, and BL4. As shown, only once an OS begins executing can the OS schedule execution of code (e.g., firmware images) on other cores such as CPU cores 112, 121, and 12].
As per claim 8, Iyengar teaches a superchip [100, fig. 1] comprising:
a compute chip [CPU 112, fig. 1].
a first chiplet [105, fig. 1].
and a second chiplet [103, fig. 1].
wherein the first chiplet comprises a central processing unit (CPU) [111, fig. 1] configured to:
load a first boot code of the first chiplet and a second boot code of the second chiplet [0033, as pointed out and shown in figure 1, the SOC 100 includes CPUSS 105 with boot loader BL1a in memory 150 as well as BL0 in memory 160].
initialize the first chiplet based on the first boot code [0033, 0035 as pointed out, the first bootloader BL1a can be initialized. For example, CPU core 111 (e.g., as initialized by BL0) executes BL1a].
and initialize the second chiplet based on the second boot code via first configuration instructions sent through the compute die [0035, 0075-0077, fig. 5 as pointed out the first processor executed some boot code where the second processor is connected to the first processor and receive service call or information to execute the next boot code. For example, in FIG. 1A, CPU core 111 (e.g., as initialized by BL0) executes BL1a. CPU core 111 further executes BL2, BL3, and BL4. As shown, only once an OS begins executing can the OS schedule execution of code (e.g., firmware images) on other cores such as CPU cores 112, 121, and 12].
As per claim 7, Iyengar teaches loading, by the CPU, a third boot code of a third chiplet of the superchip [0033, 0059 as shown in figure 1, multiple boot code can be executed].
and initializing, by the CPU, the third chiplet based on the third boot code via second configuration instructions sent through the compute die, wherein the initializing of the second chiplet and the third chiplet are performed in parallel [0059, 0079-0080, where a boot code can be executed by a processor core in parallel with other processor based on service call].
As per claims 14-15 and 20 they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 14-15 and 20 are also anticipated by Iyengar for the same reasons set forth in the rejected claims above.
To help with prosecution of the application, additional rejection is given below
Claims 1-3, 5-6, 8-10, 12-13, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghuraman (US Patent Application 20250045057).
As per claim 1, Raghuraman teaches a method [900, fig. 9] comprising:
loading, by a central processing unit (CPU) of a first chiplet of a superchip, a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip [0034, 0036, fig. 4, as pointed out the boot firmware is loaded on the appropriate chiplet such as 402 in figure 4 and 404 in figure 4. For example, the boot firmware, which can include a bootloader, initialization code, and sometimes an operating system, is loaded onto the appropriate chiplets].
initializing, by the CPU, the first chiplet based on the first boot code [0040, 0044, as pointed out one the system initialize the first chiplet with bootup sequence. For example, the subsystem initialization processes in one or more of the chiplet boot-up sequences can be ordered to reduce the interdependency between the chiplet].
initializing, by the CPU, the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip [0044-0045, as pointed out the first chiplet can send a configuration or settings signal to the second chiplet for initialization. For example, the first chiplet can send a second boot-up trigger signal 712 to the second chiplet 704. The second boot-up trigger signal 712 initiates a second boot-up sequence of the second chiplet 704. Before the second boot-up sequence of the second chiplet].
As per claim 8, Raghuraman teaches a superchip [200, fig. 3] comprising:
a compute chip [GPU: 0030].
a first chiplet [202, fig. 2].
and a second chiplet [204, fig. 4].
wherein the first chiplet comprises a central processing unit (CPU) [application processor, fig. 2 or CPU: 0030] configured to:
load a first boot code of the first chiplet and a second boot code of the second chiplet [0034, 0036, fig. 4, as pointed out the boot firmware is loaded on the appropriate chiplet such as 402 in figure 4 and 404 in figure 4. For example, the boot firmware, which can include a bootloader, initialization code, and sometimes an operating system, is loaded onto the appropriate chiplets].
initialize the first chiplet based on the first boot code [0040, 0044, as pointed out one the system initialize the first chiplet with bootup sequence. For example, the subsystem initialization processes in one or more of the chiplet boot-up sequences can be ordered to reduce the interdependency between the chiplet].
and initialize the second chiplet based on the second boot code via first configuration instructions sent through the compute die [0044-0045, as pointed out the first chiplet can send a configuration or settings signal to the second chiplet for initialization. For example, the first chiplet can send a second boot-up trigger signal 712 to the second chiplet 704. The second boot-up trigger signal 712 initiates a second boot-up sequence of the second chiplet 704. Before the second boot-up sequence of the second chiplet].
As per claim 2, Raghuraman teaches configuring the first chiplet as a main chiplet of the superchip through embedded fuse programming or hardwiring [0034, 0051 as pointed out in the multi-chiplet configuration, a chiplet can be designated to be a maser chiplet. For example, the first chiplet (e.g., chiplet 702 of FIG. 7) may be the master chiplet responsible for coordinating the overall boot-up process across all chiplets of the SoC].
As per claim 3, Raghuraman teaches the first boot code and the second boot code are loaded from an external device via a boot loader module of the first chiplet [0034, as pointed out the boot code can be loaded from a nonvolatile or flash memory. For example, the boot firmware, which can include a bootloader, initialization code, and sometimes an operating system, is loaded onto the appropriate chiplets. This firmware can be stored in non-volatile memory, such as flash memory or read-only memory (ROM) that can be located on the master chiplet or substrate 310].
As per claim 5, Raghuraman initializing the first chiplet comprises configuring internal components of the first chiplet [0039, fig. 5, initialization of processor in the chiplet].
As per claim 6, Raghuraman teaches initializing the second chiplet comprises: sending, by the CPU, the first configuration instructions to the second chiplet via an interconnection module of the compute die [0031, 0044-0045, chiplets can receive trigger signals where they communicate with each other through interconnect. For example, an interconnect structure may be formed that enables the chiplets 304, 306, 308 (e.g., in a stack of chiplets) to communicate with one another, with other chiplets mounted on the substrate 310, and with input/output structures that connect the SoC 300 with other circuits, displays, imaging sensors].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Raghuraman (US Patent Application 20250045057) in the view of Kim (US Patent Application 20170185781).
As per claim 4, Raghuraman does not teach performing, by the CPU, a security check to ensure that hardware signatures are acceptable for the first boot code and the second boot code.
However, Kim teaches performing, by the CPU, a security check to ensure that hardware signatures are acceptable for the first boot code and the second boot code [0042-0043, firmware verification integrity through digital signature].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Raghuraman to include the method of Kim to add mechanism to perform security check.
As per claims 11 and 18, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 11 and 18 are also rejected as being unpatentable over Kim in view of Raghuraman for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kwow (US 20110035575) teaches multiprocessor system comprising multi-port semiconductor memory device.
Lee (US 11620135) teaches booting method of computing system including memory module with processing device mounted.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571.270.1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
Prosecution Insights